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NAU8822A data preliminary rev 2.0 page 1 of 89 j anuary 2 5 , 20 11 NAU8822A 24 - bit stereo audio codec with speaker driver empoweraudio ? d escription the NAU8822A is a low power, high quality codec for portable and general purpose audio applications. in addition to precision 24 - bit stereo adc s and dac s, this device integ rates a broad range of additional functions to simplify impleme ntation of complete audio system solutions . the NAU8822A includes drivers for speaker , headphone , and differential or stereo line outputs, and integrates preamps for stereo differential microp hones, significantly reduc ing external component requirements. also, a fractional pll is available to accurately generate any audio sample rate for the codec using any commonly available sys tem clock from 8 mhz through 3 3mhz. advanced on - chip digital signa l processing inc ludes a 5 - band equalizer, a 3 - d audio enhancer, a mixed - signal automatic level c ontrol for the microphone or line input through the adc, and a digital limiter/dynamic - range - compressor (drc) function for the playback path . additional digital filtering options are available in the adc path, to simplify implementation of specific ap plication requirements such as wind noise reduction and speech band enhancement . the digital audio input/output interface can operate as either a master or a slav e. the NAU8822A operates with analog supply voltages from 2.5v to 3. 6 v, while the digital core can operate at 1.7 v to conserve power. the loud speaker btl output pair and two auxiliary line outputs can operate using a 5v supply to increase output power ca pability , enabling the NAU8822A to drive 1 watt into an external speaker . internal register controls enable flexible power saving modes by powering down sub - sections of the chip under software control. the NAU8822A is specified for operation from - 40c to +85c, and is available with full automotive aec - /q100 & ts16949 qualification. it is packaged in a cost - effective , space - saving 32 - lead qfn package. key features ? dac: 9 4 db snr and - 84db thd (a weighted) ? adc: 90db snr and - 80db thd (a weighted) ? int egrated btl speaker driver: 1 w into 8 ? integrated head - phone driver: 40mw into 16 ? integrated programmable microphone amplifier ? integrated line input and line output ? on - chip pll ? integrated dsp with specific functions: ? 5 - band equalizer ? 3 - d audio enhancement ? input a utomatic level contr ol (alc/agc)/limiter ? output dynamic - range - compressor/limiter ? notch filter and high pass filter ? standard audio interfaces: pcm and i 2 s ? serial control interface s with read/write capability ? rea l time readback of signal level and dsp status ? supports any sample rate f rom 8khz to 48 k hz applications ? personal media players ? smartphones ? personal navigation devices ? portable game players ? camcorders ? digital still cameras ? portable tvs ? stereo bluetooth headsets i n p u t m i x e r r a d c d a c f i l t e r v o l u m e c o n t r o l l i m i t e r a d c f i l t e r v o l u m e c o n t r o l h i g h p a s s & n o t c h f i l t e r s 5 - b a n d e q 3 d i 2 s p c m d i g i t a l a u d i o i n t e r f a c e s e r i a l c o n t r o l i n t e r f a c e o u t p u t m i x e r p l l g p i o s t e r e o m i c r o p h o n e i n t e r f a c e l a d c l d a c r d a c m i c r o p h o n e b i a s h e a d p h o n e s / l i n e d r i v e r s b t l s p e a k e r l m i c p l m i c n r m i c p r m i c n l a u x i n r a u x i n l l i n r l i n l h p r h p a u x o u t 1 a u x o u t 2 l s p k o u t r s p k o u t n a u 8 8 2 2 a y g www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 2 of 89 j anuary 25 , 20 11 empoweraudio ? p inout part number dimension package package material n au8822 a yg 5 x 5 mm 32 - qfn pb - free r l i n / g p i o 3 v s s d v d d b r s p k o u t m i c b i a s v r e f l s p k o u t 1 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 l m i c p l m i c n l l i n / g p i o 2 r m i c p r m i c n f s b c l k a d c o u t d a c i n m c l k v d d c c s b / g p i o 1 s c l k v s s s p k a u x o u t 2 a u x o u t 1 r a u x i n l a u x i n m o d e s d i o v d d a l h p r h p v s s a v d d s p k 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 2 4 2 3 2 2 2 1 2 0 1 9 1 8 1 7 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 n a u 8 8 2 2 a y g 3 2 - l e a d q f n r o h s www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 3 of 89 j anuary 25 , 20 11 empoweraudio ? pin descriptions pin # name type functionality 1 lmicp analog input left micp input (common mode) 2 lmicn analog input left micn input 3 llin/gpio2 analo g input / digital i/o left line input / alternate left micp input / gpio2 4 rmicp analog input right micp input (common mode) 5 rmicn analog input right micn input 6 rlin/gpio3 analog input / digital i/o right line input / alternate rig ht micp input / di gital output in 4 - wire mode: must be used for gpio3 7 fs digital i/o digital audio dac and adc frame sync 8 bclk digital i/o digital audio bit clock 9 adcout digital output digital audio adc data output 10 dacin digital input digital audio dac data in put 11 mclk digital input master clock input 12 vssd supply digital ground 13 vddc supply digital core supply 14 vddb supply digital buffer (input/output) supply 15 csb/gpio1 digital i/o 3 - wire mpu chip select or gpio1 multifunction input/output 16 sclk digital input 3 - wire mpu clock input / 2 - wire mpu clock input 17 sdio digital i/o 3 - wire mpu data input / 2 - wire mpu data i/o 18 mode digital input control interface mode selection pin 19 lauxin analog input left auxil i ary input 20 rauxin analog i nput right auxil i ary input 21 auxout1 analog output headphone ground / mono mixed output / line output 22 auxout2 analog output headphone ground / line output 23 rspkout analog output btl sp eaker positive output or right high current o utput 24 vssspk s upply speaker ground ( ground pin for rspkout, lspkout, auxout2 and auxtout1 output drivers ) 25 lspkout analog output btl s peaker negative output or left high current o utput 26 vddspk supply speaker supply ( power supply pin for rspkout, lspkout, auxout2 and auxtout1 output drivers ) 27 vref reference decoupling for midrail reference voltage 28 vssa supply an alog ground 29 rhp analog output headphone positive output / line output right 30 lhp analog output headphone negative output / line output left 31 vdda supply an alog power supply 32 micbias analog output microphone bias www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 4 of 89 j anuary 25 , 20 11 empoweraudio ? figure 1 : NAU8822A block diagram l d a c h p f a l c n o t c h f i l t e r l i m i t e r 5 b a n d e q 3 d a l c c o n t r o l r m i x l m i x r d a c l d a c r i n m i x r m i x l m i x l d a c l i n m i x r m a i n m i x e r l m a i n m i x e r a u x 1 m i x e r a u x 2 m i x e r l a d c m i x / b o o s t r a d c m i x / b o o s t r i n m i x l i n m i x r s p k s u b m i x e r a u x o u t 1 a u x o u t 2 l h p r h p l s p k o u t r s p k o u t l a u x i n r a u x i n l m i c n l m i c p l l i n r m i c n r m i c p r l i n v d d b v d d c v s s d v d d a v s s a v d d s p k v s s s p k b c l k f s a d c o u t d a c i n c o n t r o l i n t e r f a c e ( 2 - , 3 - a n d 4 - w i r e ) m c l k s c l k s d i o c s b / g p i o 1 m o d e v r e f r r v d d a m i c r o p h o n e b i a s m i c b i a s - 1 . 0 x + 1 . 5 x - 1 . 0 x + 1 . 5 x - 1 . 0 x + 1 . 5 x - 1 . 0 x + 1 . 5 x 1 9 2 1 4 1 3 1 2 3 1 2 8 2 6 2 4 1 3 5 4 6 2 7 2 0 3 2 2 1 2 2 3 0 2 9 2 5 2 3 a u d i o i n t e r f a c e ( p c m / i i s ) p l l 8 7 9 1 0 1 1 1 6 1 7 1 5 1 8 - + - + n o r m a l - 6 d b r d a c r a d c r a d c www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 5 of 89 j anuary 25 , 20 11 empoweraudio ? electrical characteristics conditions: vddc = 1.8v, vdda = vddb = vdd spk = 3.3v, mclk = 12.88mhz, t a = +25c, 1khz signal, fs = 48khz, 24 - bit audio data, 64x oversampling rate, unless otherwise stated. parameter symbol comments/conditions min typ max units analog to digital converter (adc) full scale input signal 1 v infs pgabst = 0db pg again = 0db 1.0 0 vrms dbv signal - to - noise ratio snr gain = 0db, a - weighted tbd 90 db total harmonic distortio n 2 thd +n input = - 3db fs input - 80 tbd db channel separation 1khz input signal 103 db digital to analog converter (dac) driving rhp / lhp with 10k? / 50pf load full - scale output gain paths all at 0db gain vdda / 3.3 v rms signal - to - noise ratio snr a - weighted 88 94 db total harmonic distortio n 2 thd +n r l = 10k?; full output mixers maximum pga gain into mixer +6 db minimum pga gain into mixer - 15 db pga gain step into mixer guaranteed monotonic 3 db speaker output ( rspkout / lspkout with 8 bridge - tied - load) full scale output 4 spkbst = 1 vccspk / 3 .3 v rms spkbst = 0 (vccspk / 3.3) * 1.5 v rms total harmonic distortion 2 thd +n p o = 200mw , vddspk=3.3v *63 db p o = 320mw , vddspk = 3.3v - 64 db p o = 860 mw, vddspk = 5v - 60 db p o = 1000 mw, vddspk = 5v - 36 db signal - to - noise ratio snr v ddspk = 3.3v 91 db vddspk=5v 90 db power supply rejection ratio (50hz - 22khz) psrr vddspk = 3.3v 81 db vddspk = 5v (boost) 72 db analog outputs ( rhp / lhp ; rspkout / lspkout ) maximum programmable gain +6 db minimum programmable gain - 57 db programmable gain step size guaranteed monotonic 1 db mute attenuation 1khz full scale signal 85 db www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 6 of 89 j anuary 25 , 20 11 empoweraudio ? electrical characteristics, contd. conditions: vddc = 1.8v, vdda = vddb = vdd spk = 3.3v, mclk = 12. 2 88mhz, t a = +25c, 1khz sign al, fs = 48khz, 24 - bit audio data, unless otherwise stated. parameter symbol comments/conditions min typ max units headphone output ( rhp / lhp with 32 load) 0db full scale output voltage avdd / 3.3 v rms signal - to - noise ratio snr a - weighted 92 db total harmonic distortion 2 thd +n r l = 16?, p o = 20mw, vdda = 3.3v 80 db r l = 32?, p o = 20mw, vdda = 3.3v 85 db auxout1 / auxout2 with 10k? / 5 0pf load full scale output aux1bst = 0 aux2bst = 0 vddspk / 3.3 v rms aux1bst = 1 aux2bst = 1 (vddspk / 3.3) * 1.5 v rms signal - to - noise ratio snr 87 db total harmonic distortio n 2 thd +n - 83 db channel separation 1khz signal 99 db power su pply rejection ratio (50hz - 22khz) psrr 53 db vddspk = 5v (boost) 56 db microphone inputs (l micp , l micn , r micp , r micn , llin, rlin) and programmable gain amplifier (pga) full scale input signal 1 pgabst = 0db pgagain = 0db 1.0 0 vrms dbv prog rammable gain - 12 35.25 db programmable gain step size guaranteed monotonic 0.75 db mute attenuation 120 db input resistance inverting input pga gain = 35.25db pga gain = 0db pga gain = - 12 db non - inverting input 1.6 47 75 94 k ? k? k? k? input boost mixer gain boost boost disabled boost enabled 0 20 db db gain range llin / rlin or lauxin / rauxin to boost/mixer - 12 6 db gain step size to boost/mixer 3 db auxiliary analog inputs (lauxin, rauxin) full scale input signal 1 gain = 0db 1.0 0 vrms dbv input resistance aux direct - to - out path, only input gain = +6.0 db input gain = 0.0db input gain = - 1 2db 20 40 159 k? k? k? www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 7 of 89 j anuary 25 , 20 11 empoweraudio ? e lectrical characteristics, contd. conditions: vddc = 1.8v, vdda = vddb = vdd spk = 3.3v, mclk = 12.88mhz, t a = +25c, 1khz signal, fs = 48khz, 24 - bit audio data, unless otherwise stated. parameter symbol comments/ conditions min typ max units automatic level control (alc) & limiter: adc path only target record level - 22.5 - 1.5 db fs programmable gain - 12 35.25 db gain hold time 3 t hold doubles every gain step, with 16 steps total 0 / 2.67 / 5.33 / / 43691 3 t dcy alc mode alc = 0 4 / 8 / 16 / / / / 3 t atk alc mode alc = 0 1 / 2 / 4 / / / / 1 microphone bias bias voltage v micbias see figure 3 0.50, 0.60,0.65, 0.70, 0.75, 0.85, or 0.90 vdda vdda bias current source i micbias 3 ma output noise voltage v n 1khz to 20khz 1 4 nv/hz digital input/output input high level v il 0.7 * vddc v input low level v ih 0.3 * vddc v output high level v oh i load = 1ma 0.9 * vddc v output low level v ol i l o ad = - 1ma 0.1 * vddc v input capacitance 10 pf notes 1. full scale is relative to the magnitud e of vdd a and can be calculated as fs = vdd a/3.3. 2. distortion is measured in the standard way as the combined quantity of distortion products plus noise. the signal level for distortion measurements is at 3db below full scale, unless otherwise noted. 3. time values scale proportionally with mclk. complete descriptions and definitions for these values are contained in the detailed descriptions of the alc functionality. 4. with default register settings, spkvdd should be 1.5xvdda (but not exceeding maximum recomme nded operating voltage) to optimize available dynamic range in the auxout1 and auxout2 line output stages. output dc bias level is optimized for spkvdd = 5.0vdc (boost mode) and vdda = 3.3vdc. 5. unused analog input pins should be left as no - connection. 6. unus ed digital input pins should be tied to ground. www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 8 of 89 j anuary 25 , 20 11 empoweraudio ? absolute maximum ratings condition min max units v ddb , v ddc , v dda supply voltages - 0.3 +3.61 v v ddspk supply voltage (default register configuration) - 0.3 +5.8 0 v v ddspk supply voltage (optional low vol tage configuration) - 0.3 +3.61 v core digital input voltage range v ssd C 0.3 v ddc + 0.30 v buffer digital input voltage range v ssd C 0.3 v ddb + 0.30 v analog input voltage range v ssa C 0.3 v dda + 0.30 v industrial operating temperature - 40 +85 c s torage temperature range - 65 +150 c caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adversely influence product reliability and result in failures not covered by warranty. opera ting conditions condition symbol min typical max units digital supply range (core) v ddc 1. 65 3.60 v digital supply range (buffer) v ddb 1. 65 3.60 v analog supply range v dda 2.50 3.60 v speaker supply (spkbst=0) v ddspk 2.50 5.50 v speaker supply (sp kbst=1) v ddspk 2.50 5.50 v ground v ssd v ssa v ssspk 0 v 1. v dda must be v ddc . 2. v ddb must be v ddc . www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 9 of 89 j anuary 25 , 20 11 empoweraudio ? table of contents 1 general description ................................ ................................ ................................ ............................. 11 2 power supply ................................ ................................ ................................ ................................ ............. 13 3 input path detailed descriptions ................................ ................................ ................................ .. 14 3.1 programmable gain amplifier (pga) ................................ ................................ ................................ ......... 14 3.2 positive microphone input (micp) ................................ ................................ ................................ .............. 15 3.3 negative microphone input (micn) ................................ ................................ ................................ ............ 16 3.4 microphone biasing ................................ ................................ ................................ ................................ .... 17 3.5 line/aux input impedance and variable gain stage topology ................................ ................................ .. 17 3.6 left and right line inputs ( llin and rlin) ................................ ................................ ............................... 19 3.7 auxiliary inputs (lauxin, rauxin) ................................ ................................ ................................ ........... 19 3.8 adc mix/boost stage ................................ ................................ ................................ ................................ . 19 3.9 input limiter / automatic level control (alc) ................................ ................................ ............................ 20 3.10 alc peak limiter function ................................ ................................ ................................ ......................... 22 3.11 noise gate (no rmal mode only) ................................ ................................ ................................ ................ 22 3.12 alc example with alc min/max limits and noise gate operation ................................ ........................... 24 3.13 limiter mode ................................ ................................ ................................ ................................ .............. 25 4 adc digital block ................................ ................................ ................................ ................................ .. 26 4.1 sampling / oversampling rate, polarity control, digital passthrough ................................ ....................... 26 4.2 adc digital volume control and update bit functionality ................................ ................................ ......... 27 4.3 adc programmable high pass filter ................................ ................................ ................................ ......... 27 4.4 progr ammable notch filter ................................ ................................ ................................ ........................ 27 5 dac digital block ................................ ................................ ................................ ................................ .. 29 5.1 dac soft mute ................................ ................................ ................................ ................................ ........... 29 5.2 dac automute ................................ ................................ ................................ ................................ ........... 29 5.3 dac sampling / oversampling rate, polarity control, digital passthrough ................................ ............... 29 5.4 dac digital volume co ntrol and update bit functionality ................................ ................................ ......... 30 5.5 dac automatic output peak limiter / volume boost ................................ ................................ ................. 30 5.6 5 - band equalizer ................................ ................................ ................................ ................................ ........ 31 5.7 3d stereo enhancement ................................ ................................ ................................ ............................ 32 5.8 companding ................................ ................................ ................................ ................................ ............... 32 5.9 - law ................................ ................................ ................................ ................................ .......................... 32 5.10 a - law ................................ ................................ ................................ ................................ .......................... 32 5.11 8 - bit word length ................................ ................................ ................................ ................................ ....... 33 6 analog outputs ................................ ................................ ................................ ................................ ....... 34 6.1 main mixers (lmain mix and rmain mix) ................................ ................................ ............................... 34 6.2 auxiliary mixers (aux1 mixer and aux2 mixer) ................................ ................................ .................... 34 6.3 right speaker submixer ................................ ................................ ................................ ............................ 35 6.4 headphone outputs (lhp and rhp) ................................ ................................ ................................ ......... 35 6.5 speaker outputs ................................ ................................ ................................ ................................ ........ 36 6.6 auxiliary outputs ................................ ................................ ................................ ................................ ........ 37 7 miscellaneous functi ons ................................ ................................ ................................ .................. 37 7.1 slow timer clock ................................ ................................ ................................ ................................ ....... 37 7.2 general purpose inputs and outputs (gpio1, gpio2, gpio3) and jack detection ................................ . 38 7.3 automated features linked to jack detection ................................ ................................ ........................... 38 8 clock selection and generation ................................ ................................ ................................ .. 39 www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 10 of 89 j anuary 25 , 20 11 empoweraudio ? 8.1 phase locked loop (pll) general description ................................ ................................ ......................... 40 8.2 csb/gpio1 as pll output ................................ ................................ ................................ ......................... 41 9 control interfaces ................................ ................................ ................................ .............................. 42 9.1 selection of control mode ................................ ................................ ................................ .......................... 42 9.2 2 - wire - serial control mode (i 2 c style interface) ................................ ................................ ........................ 42 9.3 2 - wire protocol convention ................................ ................................ ................................ ....................... 42 9.4 2 - wire write operation ................................ ................................ ................................ ............................... 43 9.5 2 - wire read operation ................................ ................................ ................................ .............................. 44 9.6 spi control interface modes ................................ ................................ ................................ ...................... 44 9.7 spi 3 - wire write operation ................................ ................................ ................................ ........................ 45 9.8 spi 4 - wire 24 - bit write and 32 - bit read operation ................................ ................................ ................... 45 9.9 spi 4 - wire write operation ................................ ................................ ................................ ...................... 45 9.10 spi 4 - wire read operation ................................ ................................ ................................ ........................ 46 9.11 software reset ................................ ................................ ................................ ................................ ........... 46 10 digital audio interf aces ................................ ................................ ................................ ................... 47 10.1 right - justified audio data ................................ ................................ ................................ .......................... 47 10.2 left - justified audio data ................................ ................................ ................................ ............................ 47 10.3 i 2 s audio data ................................ ................................ ................................ ................................ ............ 48 10.4 pcm a audio data ................................ ................................ ................................ ................................ ..... 48 10.5 pcm b au dio data ................................ ................................ ................................ ................................ ..... 49 10.6 pcm time slot audio data ................................ ................................ ................................ ........................ 49 10.7 control interface timing ................................ ................................ ................................ ............................. 51 10.8 audio interface timing: ................................ ................................ ................................ .............................. 53 11 application informat ion ................................ ................................ ................................ ................... 54 11.1 typical application schematic ................................ ................................ ................................ .................... 54 11.2 recommended power up and power down sequences ................................ ................................ .............. 55 11.3 power consumption ................................ ................................ ................................ ................................ ... 58 11.4 supply currents of specific blocks ................................ ................................ ................................ ............. 59 12 appendix a: digital filter characteristi cs ................................ ................................ ............ 60 13 appendix b: compand ing tables ................................ ................................ ................................ ..... 65 13.1 - law / a - law codes for zero and full scale ................................ ................................ ............................ 65 13.2 - law / a - law output codes (digital mw) ................................ ................................ ................................ . 65 14 appendix c: details of register operatio n ................................ ................................ .............. 66 15 appendix d: registe r overview ................................ ................................ ................................ ....... 86 16 package dimensions ................................ ................................ ................................ .............................. 88 17 ordering information ................................ ................................ ................................ ......................... 89 www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 11 of 89 j anuary 25 , 20 11 empoweraudio ? 1 general description the NAU8822A is an upgrade to the wau8822 , and delivers reduced out - of - band noise energy , improved alc and dsp signal processing, read - out capabili ty of realtime signal level, readout of dsp status, and added controls for industry leading pop/click noise management. additionally, handling of settings for 5 - volt and 3 - volt operation are simpl ified, and all registers unique to nuvoton are moved to higher addresses. this makes the part a direct hardware and software drop - in replacement for common industry parts. the NAU8822A is a stereo part with identical left and right channels that share com mon support elements. additionally, the right channel auxiliary output path includes a dedicated sub mixer that s upports mixing the right auxiliary input directly into the right speaker output driver. this enables the right speaker channel to output audio that is not present on any other output. 1.1.1 analog inputs all inputs, except for the wide range programmable amplifier (pga), have available analog input gain conditioning of - 15db through +6db in 3db steps. all inputs also have individual muting functions with excellent channel isolation and off - isolation from all outputs. all inputs are suitable for full quality, high bandwidth signals. each of the left - right stereo channels includes a low noise differential pga amplifier , programmable for high - gain input . this may be used for a microphone level through line level so urce. gain may be set from +35.2 5db through - 12db at the analog difference - amplifier type programmable ampli fi er input stage. a separate additional 20db analog gain is available on this i nput path, between the pga output and adc mixer input. the output of the adc mixer may be routed to the adc and/or analog bypass to the analog output sections. each channel also has a line level input. this input may be routed to the input pga, and/or di rectly to the adc input mixer. e ach channel has a separate additional auxiliary input. this is a line level input which may be routed the adc input mixer and/or directly to the analog output mixers. 1.1.2 analog outputs there are six high current analog audio o utputs. these are very flexible outputs that can be used individually or in stereo pairs for a wide range of end uses. however, these outputs are optimized for specific functions and are described in this section using the functional names that are appli cable to those optimized functions. each output receives its signal source from built - in analog output mixers. these mixers enable a wide range of signal combinations, including muting of all sources. additionally, each output has a programmable gain fun ction, output mute function, and output disable function. the rhp and lhp headphone outputs are optimized for driving a stereo pair of he adphones, and are powered from the main analog voltage supply rail, vdda. these outputs may be coupled using tradition al dc blocking s eries capacitors . alter n atively, these may be configured in a no - capacitor dc coupled design using a virtual ground at ? vdda prov ided by an auxout analog output operating in the non - boost output mode . the auxout1 and auxout2 analog output s are powered from the vddspk supply rail and vssspk ground return path . the supply rail may be the same as vdda , or may be a separate voltage up to 5 .5 vdc. this higher voltage enables these o utputs to have an increased output voltage range and greater o utput power capability. the rspkout and lspkout louds peaker outputs are powered from the vddspk power supply rail and vssgnd ground return path . lspkout receives its audio signal via an additional submixer. this submixer supports combining a traditional alert sound (from the rauxin input) with the right channel headphone output mixer signal. this submixer also provides the signal invert function that is necessary for the normal btl ( bridge tied load ) configuration used to drive a high power external lou dspeaker. alternatively, each loud speaker output may be used individually as a separate high current analog output driver. a programmable low - noise micbias microphone bias supply output is included. this is suitable for both conventional electret (ecm) type microphone, and to power the newer mems all - silicon type microphones. www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 12 of 89 j anuary 25 , 20 11 empoweraudio ? 1.1.3 adc, dac, and digital signal processing each left and right channel has an independent high quality adc and dac associated with it. these are high performance , 24 - bit delta - sigma converters that are suitab le for a very wide range of applications. the adc and dac functions are each individually supported by powerful analog mixing and routing. the adc output may be routed to the digital output path and/or to the input of the dac in a digital passthrough mode. the adc and dac blocks are also supported by advanced digital signal processing subsystems that enable a very wide range of programmable signal conditioning and signal optimizing functions. all digital processing is with 24 - bi t precision, as to minimize processing artifacts and maximize the audio dynamic r ange supported by the NAU8822A . the adcs are supported by a wide range, mixed - mode automatic level control (alc), a high pass filter, and a notch filter. all of these feature s are optional and highly programmable. the hig h pass filter function is intend ed for dc - blocking or low frequency noise reduction, such as to reduce unwanted ambient noise or wind noise on a microphone input. the notch filter may be programmed to grea tly reduce a specific frequency band or frequency , such as a 50hz, 60hz, or 217hz unwanted nois e. the dacs are supported by a programmable limiter/drc (dynamic range compressor). this is useful to optimize the output level for various applications and for use with small loudspeakers. this is an optional feature that may be programmed to limit the maximum output level and/or boost an output level that is too small. digital signal processing is also provided for a 3d audio enhancement function , and for a 5 - band equalizer. these features are optional , and are programmable over wide ranges. this pair of digital processing features may be applied jointly to either the adc audio path or to the dac audio path, but not to both paths simultaneously. 1.1.4 realtime sign al level readout and dsp status in addition to general read - back ability of all its registers, the NAU8822A includes powerful capalities to readback signal related dsp information not possible with almost any other codec. in conjunction with the alc, the software by means of the readback function can determine the realtime signal level at the inputs, as well as the realtime actual gain setting being used by the alc. additionally, other signal related information can also be determined, such as the noise g ate on/off status and automute/softmute function status. these greatly enhance both the ability to optimize software and to enhance dynamic end product functionality. 1.1.5 d igital interfaces command and control of the device is accomplished using a 2 - wire/3 - wi re /4 - wire serial control interface. this is a simple, but highly flexible interface that is compatible with many commonly used command and control serial data protocols and host drivers. digital audio input/output d ata streams are transferred to and from the device separately from command and control. the digital a udio data interface supports either i2s or pcm audio data protocols, and is compatible with commonly used industry standard devices that follow either of these two serial data formats. 1.1.6 c lock req uirements the clocking signals required for the audio signal processing, audio data i/o, and control logic may be provided externally, or by optional operation of a built - in pll (phase locked loop) . the pll is provided as a low cost, zero external compon ent count optional method to generate required clocks in almost any system. the pll is a fractional - n divider type design, which enables generating accurate desired audio sample rates derived from a very wide range of commonly available system clocks. the frequency of the system clock provided as the pll reference frequency may be any stable frequency in the range between 8mhz and 33mhz. because the fractional - n multiplication factor is a very high precision 24 - bit value, any desired sample rate supported by the NAU8822A can be generated with very high accuracy, typically limited by the accuracy of the external reference frequency. reference clocks and sample rates outside of these ranges are also possible, but may involve performance tradeoffs and increa sed design verification. www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 13 of 89 j anuary 25 , 20 11 empoweraudio ? 2 power supply t his device has been designed to operate reliably using a wide range of power supply conditions and power - on/power - off sequences. t here are no special requirements for the sequence or rate at which the various power supply pins change. any supply can rise or fall at any time without harm to the device. however, pops and clicks may result from some sequences. optimum handling of hardware and software power - on and power - off sequencing is described in more detail in t he applications section of this document. 2.1.1 power - on reset the NAU8822A does not have a n external reset pin. the device reset function is automatically generated internally when power supplies are too low for reliable operation. the internal reset is gener ated any time that either vdda or vddc is lower than is required for reliable maintenance of internal logic conditions. the reset threshold volta ge for vdda and vddc is approximately 0.5vdc. if both vdda and vddc are being reduced at the same time, the t hreshold voltage may be slightly lower. note that these are much lower voltages than are required for normal operation of the chip. these values are mentioned here as general guidance as to overall system design. if either vdda or vddc is below its respe ctive threshold voltage, an internal reset condition is asserted. during this time, all registers and controls are set to the hardware determined initial conditions. software access during this time will be ignored, and any expected actions from software activity will be invalid. when both vdda and vddc reach a value above their respective thresholds, an internal reset pulse is generated which extends the reset condition for an additional time. the duration of this extended reset time is approximately 50 microseconds, but not longer than 100 microseconds. the reset condition remains asserted during this time. if either vdda or vddc at any time becomes lower than its respective threshold voltage, a new reset condition will result. the reset condition wi ll continue until both vdda and vddc again higher than their respective thresholds. after vdda and vddc are again both greater than their respective threshold voltage, a new reset pulse will be generated, which again will extend the reset condition for no t longer than an additional 100 microseconds. 2.1.2 power related software considerations there is no direct way for software to determine that the device is actively held in a reset condition. if there is a possibility that software could be accessing the devi ce sooner than 100 microseconds after the vdda and vddc supplies are valid, the reset condition can be determined indirectly. this is accomplished by writing a value to any register other than register 0x00, with that value being different than the power - on reset initial values. the optimum choice of register for this purpose may be dependent on the system design, and it is recommended the system engineer choose the register and register test bit for this purpose. after writing the value, software will t hen read back the same register. when the register test bit reads back as the new value, instead of the power - on reset initial value, software can reliably determine that the reset condition has ended. although it is not required, it is strongly recommend ed tha t a software reset command should be issued after power - on and after the power - on reset condition is ended. this will help insure reliable operation under every power sequencing condition that could occur. if there is any possibility that vdda or vd dc could be unreliable during system operation, software may be designed to monitor whether a power - on reset condition has happened. this can be accomplished by writing a test bit to a register that is different from the power - on initial conditions. this test bit should be a bit that is never used for any other reason, and does not affect desired operation in any way. then, software at any time can read this bit to determine if a power - on reset condition has occurred. if this bit ever reads back other t han the test value, then software can reliably know that a power - on reset event has occurred. software can subsequently re - initialize the device and the system as required by the system design. 2.1.3 software reset all chip registers can be reset to power - on de fault conditions by writing any value to register 0, using any of the control modes. writing valid data to any other register disables the reset, but all registers need to have the correct operating data written. see the applications section on powering NAU8822A up for information on avoiding pops and clicks after a software reset. www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 14 of 89 j anuary 25 , 20 11 empoweraudio ? 3 input path detailed descriptions the NAU8822A provides multiple inputs to acquire and process audio signals from microphones or other sources with high fidelity and flexibilit y. there are left and right input paths, each with three input pins, which can be used to capture signals from single - ended, differential or dual - differential microphones. these input channels each include a programmable gain amplifier (pga). the output s of the pgas, plus two additional auxiliary inputs, are then connected to the input boost/mix stages for maximum flexibility handling various signal sources. all inputs are maintained at a dc bias at approximately ? of the avdd supply voltage. connection s to these inputs should be ac - coupled by means of dc blocking capacitors suitable for the device application. d if ferential microphone input (micn & micp pins) and programmable gain amplifier the NAU8822A features a low - noise, high common mode rejection ra tio (cmrr), differen tial microphone input pair, micp and mic n , which are connected to a pga g ain stage. the differential input structure is essential in noisy digital systems where amplification of low - amplitude analog signals is necessary such as in port able digital media devices and cell phones . diff erential inputs very useful to reduce ground noise in systems in which there are ground voltage differences between different chips and other components. when properly implemented, the differential input ar chitecture offers an improved power - supply rejection ratio (psrr) and higher ground noise immunity. 3.1 programmable gain amplifier (pga) each pga supp orts three possible inputs, micp, micn , and lin. these are the microphone differential pair and a separate line level input. the pga has a gain range of - 12db through +35.25db in evenly spaced decibel increments of 0.75db. operation of the pga is subject to control by the following registers: r2 power management con trols for the left and right pga r2 power ma nagement controls for adc mix/boost (must be on for any pga path to function) r7 zero crossing timeout control r32 automatic level control (alc) for the left and right pga r44 input selection options for the left and right pga r45 volume (gain), mute, up date bit, and zero crossing control for the left pga r46 volume (gain), mute, update bit, and zero crossing control for the right pga i mportant : the r45 and r46 update bits are write - only bits. the primary intended purpose of the update bit is to enable simultaneous changes to both the left and right pga volume values, even though these values must be written sequentially. when there is a write operation to either r45 or r46 volume settings, but the update bit is not set (value = 0) , the new volume setti ng is stored as pending for the future, but does not go into effect. when there is a write operation to either r45 or r46 and the update bit is set (value = 1), then the new value in the register being written is immediately put into effect, and any pendi ng value in the other pga volume register is put into effect at the same time. note: if the alc automatic level control is enabled, the function of the alc is to automatically adjust the r45 or r46 volume setting. if alc is enabled for the left or right, or both channels, then software should avoid changing the volume setting for the affected channel or channels. the reason for this is to avoid unexpected volume changes caused by competition between the alc and the direct software control of the volume s etting. zero - crossing controls are implemented to suppress clicking sounds that may occur when volume setting changes take place while an audio input signal is active. when the zero crossing function is enabled (logic = 1), any volume change for the affec ted channel will not take place until the audio input signal passes through the zero point in its peak - to - peak swing. this prevents any instantaneous voltage change to the audio signal caused by volume setting changes. if the zero crossing function is di sabled (logic = 0), volume changes take place instantly on condition of the update bit, but without regard to the instantaneous voltage level of the affected audio input signal. the r7 zero crossing timeout control is an additional feature to limit the amo unt of time that a volume change to the pga is delayed pending a zero crossing event. if the input signal is such that there are no zero crossing events, and the timeout control is enabled (level = 1), any new volume setting to either pga will automatical ly be put into effect after between 2.5 and 3.5 periods of the slow timer clock (see description under miscellaneous functions). www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 15 of 89 j anuary 25 , 20 11 empoweraudio ? 3.1.1 zero crossing example this drawing shows in a graphical form the problem and benefits of using the zero crossing feature. th ere is a major audible improvement as a result of using the zero crossing feature. figure 2 : zero crossing gain update operation figure 3 : pga i nput structure simplified schematic 3.2 positive microphone input (micp ) the positive (non - inverting) microphone input (micp ) can be used separately, or as part of a differential input configuration. this input pin connects to the positive (non - inverting) ter minal o f the pga amplifier under control of register r44. when the r44 associated control bit is set (lo gic = 1), a switch connects micp to the pga input. when the associated control bit is not set (logic = 0), th e micp pin is connected to a resistor of approximately 30 k which is tied to vref. the purpose of the tie to vref is to reduce any pop or click sound by keeping the dc level of the micp pin close to vref at all times. note: if the micp signal is not used differentially with micn , the pga gain values will be va lid only if the micn pin is terminated to a low impedance signal point. this termination should normally be an ac coupled path to signal ground. this input impedance is constant regardless of the gain value. the nominal input impedance for this input is given by the following table. impedance for specific gain values not listed in this table can be estimated through interpolation between listed values. g a i n c h a n g e p g a i n p u t p g a o u t p u t w i t h z e r o c r o s s e n a b l e d p g a o u t p u t w i t h z e r o c r o s s d i s a b l e d r m i c p m i c n - 1 2 d b t o + 3 5 . 2 5 d b t o a d c m i x / b o o s t p g a g a i n r 4 5 , r 4 6 i n p u t s e l e c t i o n r 4 4 r r v r e f l i n r v r e f www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 16 of 89 j anuary 25 , 20 11 empoweraudio ? nominal input impedance gain (db) impedance (k) lmicp & rmicp to non - inverting pga input or llin & rlin to non - inverting pga input - 12 94 - 9 94 - 6 94 - 3 94 0 94 3 94 6 94 9 94 12 94 18 94 30 94 35.25 94 table 1 : microphone and line non - inverti ng input impedances 3.3 negative microphone input (mic n ) the negative (inverting) microphone input ( micn ) can be used separately, or as part of a differential input configuration. this input pin connects to the negative ( inverting) terminal o f the pga amplifi er under control of register r44. when the r44 associated control bit is set (logic = 1), a switch connects micp to the pga input. when the associated control bit is not set (logic = 0), the micn pin is connected to a resistor of approximately 30 k which is tied to vref. the purpose of the tie to vref is to reduce any pop or click sound by keeping the dc level of the micn pin close to vref at all times. it is important for a system designer to know that the micn input impedance varies as a functi on of the selected pga gain. this is normal and expected for a difference amplifier type topology. the nominal resistive impedance values for this input over the possible gain range are given by the following table. impedance for specific gain values no t listed in this table can be estimated through interpolation between listed values. nominal input impedance gain (db) impedance (k) lmicn or rmicn to inverting pga input - 12 75 - 9 69 - 6 63 - 3 55 0 47 3 39 6 31 9 25 12 19 18 11 30 2.9 35.25 1.6 table 2 : microphone inverting input impedances system designers should also note that at t he highest gain values, the input impedance is relatively low. for most inputs, the best strategy if higher gain values are needed is to use the input pga in combination with the +20db gain boost available on the pga mix/boost stage tha t immediately follo ws the pga output. a good guideline is to use the pga gain for up to around 20db of gain. if more gain than this is required and the lower input impedance of the pga at high gains is a problem, a combination of the pga and boost stage should be used. i n this type of combined gain configuration, it is preferred to have at least 6db gain at the pga input stage to benefit from the pga low noise characteristics. www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 17 of 89 j anuary 25 , 20 11 empoweraudio ? 3.4 microphone biasing the micbias pin provides a low - noise microphone dc bias voltage as may be req uired for operation of an external microphone. this built - in feature can typically provide up to 3ma of microphone bias current. this dc bias voltage is suitable for powering either traditional ecm (electret) type microphones, or for mems types microphon es with an independent power supply pin. seven differen t bias voltages are available f or optimum system performance , depending on the specific application. the microphone bias pin normally requires an external filtering capacitor as shown on the schematic in the application section. the microphone bias function is controlled by the following registers: r1 power control for micbias feature (enabled when bit 4 = 1) r 58 optional low - noise mode and different bias voltage levels (enabled when bit 0 = 1 ) r44 primary micbias voltage selection the low - noise feature results in greatly reduced noise in the extern al micbias voltage by placing a resistor of approximately 200 - ohms in series with the output pin. this creates a low pass filter in conjunction with the external micbias filter capacitor, but without any additional external components. the low noise feat ure is enabled when the mo de control bit 0 in register r 58 is set (level = 1) figure 4 : mi crophon e bias generator 3.5 line/aux input impedance and variable gain stage topology except for the input pgas, other variable gain stages are implemented similarly to the simplified schematic shown here. the gain value changes affect input impedance in the ranges detailed in the description of each type of input path. if a path is in the not selected condition, then the input impedance will be in a high impedance condition. if an external input pin is not used anywhere in the system, it will be coupled to a dc tie - off of approximately 30 k coupled to vref. the unused input/output tie - off function is explained in more detail in the application information section of this document. figure 5 : variable gain st age simplified schematic r v r e f r m i c b i a s r e g i s t e r 1 , b i t 4 m i c b i a s e n r e g i s t e r 4 0 , b i t 0 m i c b i a s m r e g i s t e r 4 4 , b i t s 7 - 8 m i c b i a s v r e g i s t e r 4 4 , b i t s 7 - 8 0 0 0 1 1 0 1 1 0 0 1 1 1 0 0 1 r e g i s t e r 5 8 , b i t 0 1 1 1 1 0 0 0 0 m i c r o p h o n e b i a s v o l t a g e 0 . 9 0 * v d d a 0 . 6 5 * v d d a 0 . 7 5 * v d d a 0 . 5 0 * v d d a 0 . 8 5 * v d d a 0 . 6 0 * v d d a 0 . 7 0 * v d d a 0 . 5 0 * v d d a r i n p u t - 1 5 d b t o + 6 . 0 d b t o n e x t s t a g e g a i n v a l u e a d j u s t m e n t n o t s e l e c t e d s w i t c h r v r e f www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 18 of 89 j anuary 25 , 20 11 empoweraudio ? the input impedance presented to these inputs depends on the input routing choices and gain values. if an input is routed to more than one internal input node, then the effective input impedance will be the parallel combination of the impedance of the multiple nodes that are used. the impedance looking into the pga non - inverting input is constant as listed in the section discussing the microphone input pgas. the nominal resistive input impedances looking into the adc mix/boost input inputs are listed in the following table: inputs gain (db) impedance (k) not selected high - z lauxin & rauxin to l/radc mix/boost amp or llin & rlin to l/radc mix/boost amp - 12 159 - 9 113 - 6 80 - 3 57 0 40 3 28 6 20 table 3 : mix/boost amp impedances the nominal resistive input impedances presented to signal pins that are directly routed to an output mixer are listed in the following table. if an input is connected to other active nodes, then this value is in p arallel with the resistive input impedance of any such other node. inputs gain (db) impedance (k) lauxin & rauxin to bypass amp or rauxin to rspk submixer amp - 15 225 - 12 159 - 9 113 - 6 80 - 3 57 0 40 3 28 6 20 table 4 : bypass amp and rspk submixer input impedances www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 19 of 89 j anuary 25 , 20 11 empoweraudio ? 3.6 left and right line inputs (llin and rlin ) a third possible input to the left or right pga is an optional associated lin left or right line level input. these inputs may be routed to the pga non - inverting input, and/or connect directly to the adc mixer/boost stage. if routed to the pga, thi s s ignal is processed as an alternate pin for the micp signal. lin may be received differentially in relation to the micn pin and has available the sam e gain range as for micp . a s in the operational case of using the micp input, the micn input must have a l ow impedance path to signal ground, so that the gain values chosen in the pga are valid. note: it not recommended that both the lin line input path to the pga and the micp path to the pga be enabled at the same time. this will cause the differential gain to be unbalanced , and result in poor common mode rejection. also, this will result in the lin and micp signals being connected together through internal chip resistors. the line input pins, may alternatively be configured to operate as a gpio (general pu rpose input/output) logic input pin . this intended purpose is static logic voltage level sensing to determine if a headset is present or not as part of a physical detection of a possible external headset. only one gpio pin at any one time can be assigned for this purpose. registers that affect operation of the llin and rlin inputs are: r2 adc mix/boost power control (must be on for any lin path to function) r9 gpio selection for headset detect function r44 pga input selection control bits if selected, a ll other pga control registers (see pga description) r 47 left line input adc mix/boost volume and mute (bits 4, 5, and 6) r48 right line input adc mix/boost volume and mute (bits 4, 5, and 6) 3.7 auxiliary inputs (lauxi n, rauxin) the left and right channels ea ch have an additional input that is separate from the programmable amplif i er stage. these are the left and right auxiliary inputs, lauxin and rauxin. these inputs may be routed to either or both the associated adc mix/boost stage , or the a ssociated lch m ix or rch mix output mixer. the rauxin input may add itionally be routed to the right speaker submixer in the analog output section. this path enables a sound to be output from the lspkout speaker output, but without being audible anywhere else in the syst em. one purpose of this path is to support a traditional beep sound, such as from a microprocessor toggle bit. this is a historical application scenario which is now uncommon. the auxiliary inputs are affected by the following registers: adc mix/boos t if used (see adc mix/boost section) lch mixer or rch mixer if used (see output mixer section) beep mixer if used (see beep mixer section) note: no power control registers affect only the auxiliary inputs the input impedance presented to these inputs dep ends on the input routing choices and gain values. if an input is routed to more than one internal input node, then the effective input impedance will be the parallel combination of the impedance of the multiple nodes that are used. the input impedances presented to these inputs are the same as those listed for the llin and rlin inputs. 3.8 adc mix /boost stage the left and right channels each have an independent adc mix/boost stage. most analog input signals must pass through the adc mix/boost stage before use anywhere else in this device. the only analog inputs that can completely bypass the adc mix/boost stage are the lauxin and rauxin auxiliary inputs. the adc mixer stage has three inputs , aux, lin, and pga. the aux input is for the associated auxiliary input, and the lin is for the associated line input. the pga input is an internal connection to the associated programmable gain amplifier servicing the microphone and line inputs. www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 20 of 89 j anuary 25 , 20 11 empoweraudio ? all three inputs to the adc mix/boost stage can be independently muted, a nd all three inputs have independent gain controls. the aux and lin inputs have an available gain range of - 12db through +6 db in 3db steps. the pga input path has a choice of 0db or 20db of gain in addition to the gain in the pga. registers that affect t he adc mix/boot stage are: r2 power control for left and right channels r45 mute function for left channel pga (bit 6 = 0 = muted condition) r46 mute function for right channel pga (bit 6 = 0 = muted condition) r47 gain and mute control for left channel au x and lin r48 gain and mute control for right channel aux and lin 3.9 input limiter / automatic level control (alc) the input section of the NAU8822A is supported by additional combined digital and analog functionality which implement an automatic level contro l ( alc) function. this can be very useful to automatically manage the analog input gain to optimize the signal level at the output of the programmable amplifier. the alc can automatically amplify input signals that are too small, or decrease the amplitud e if the signals are too loud. this system also helps to prevent clipping (overdrive) at the input of the adc while maximizing the full dynamic range of the adc . the alc may be operated in the normal mode just described, on in a special limiter mode of o peration. the limiter mode is a faster mode of operation, the primary purpose of which is to limit too - loud signals. the limiter mode of operation is described after this section which provides details on the normal mode of operation. the functional bloc k architecture for the alc is shown below. the alc monitors the output of the adc, measured after the digital decimator . the adc output is fed into a peak detector, which updates the measured peak value whenever the absolute value of the input signal is higher than the current measured peak. the measured peak gradually decays to zero unless a new peak is detected, allowing for an accurate measurement of the signal envelope. the peak value is used by a logic algorithm to determine whether the pga input g ain should be increased, decreased, or remain the same. figure 6 : alc block diagram 3.9.1 normal mode example operation immediately following is a simple example of the alc operation. in the steady state a t the beginning of the example time sequence, the pga gain is at a steady value which results in the desired output level from the adc. when the input signal suddenly becomes louder, the alc reduces volume at a register determined rate and step size. thi s continues until the output level of the adc is again at the desired target level. when the input signal suddenly becomes quiet, the alc increases volume at a register determined rate and step size. when the output level from the adc again reaches the t arget level, and now the input remains at a constant level, the alc remains in a steady state. p g a a d c f i l t e r d i g i t a l d e c i m a t o r a l c r a t e c o n v e r t / d e c i m a t o r www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 21 of 89 j anuary 25 , 20 11 empoweraudio ? figure 7 : alc normal mode operation 3.9.2 alc parameter defin i tions automatic level and volume control features are complex and have difficult to understand traditional names for many features and controls. this section defines some terms so that the explanations of this subsystem are more clear. alc maximum gain: register 32 (alcm xgai n) this sets the maximum a llowed gain in the pga during normal mode alc operation. in the limiter mode of alc operation, t he alcm xgain value is not used . in the limiter mode, the maximum gain allowed for the pga is set equal to the pre - existing pga gain value that was in effect a t the moment in time that the limiter mode is enabled. alc minimum gain : register 32 (alcmngain) this sets the minimum allowed gain in the pga during all modes of alc operation. this is useful to keep the agc operating range close to the desired range f or a given application scenario. alc target value : register 33 (alcsl) determines the value used by the alc logic decisions comparing this fixed value with the output of the adc. this value is expressed as a fraction of full scale (fs) output from the a dc. depending on the logic conditions, the output value used in the comparison may be either the instantaneous value of the adc, or otherwise a time weighted average of the adc peak output level. alc attack time : register 34 (alcatk) attack time refers to how quickly a system responds to an increasing volume level that is greate r than some defined threshold. typically, attack time is much faster than decay time. in the NAU8822A , w hen the absolute value of the adc outp ut exceeds the alc target value, the pga gain will be reduced at a step size and rate determined by this parameter. when the peak adc output is at least 1.5db lower than the alc target value, the stepped gain reduction will halt. alc decay time : register 34 (alcdcy) decay time refers t o how quickly a system responds to a decreasing volume level. typically, decay time is much slower than attack time. when the adc output level is below the alc target value by at least 1.5db, the pga gain will increase at a rate determined by this parame ter. the decay tim e constant is determined by the setting in register 34, bits 4 to 7 (alcdcy), which sets the delay between increases in gain . in l imiter mode, the time constants are faster than in alc mode . (see detailed register map.) alc hold time r egister 33 (alchld) hold time refers to a duration of time when no action is taken. this is typically to avoid undesirable sounds that can happen when an alc responds too quickly to a changing input signal. the use and amount of hold time is very applic ation specific. in the NAU8822A , the hold time value is the duration of time that the adc output peak value must be less than the target value before there is an actual gain increase. p g a i n p u t p g a o u t p u t p g a g a i n www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 22 of 89 j anuary 25 , 20 11 empoweraudio ? 3.10 alc peak limiter function to reduce clipping and other bad audio effect s, all alc modes include a peak limiter function. this implements an emergency pga gain reduction when the adc output level exceeds a built - in maximum value. when the adc output exceeds 87.5% of full scale, the alc block ramps down th e pga gain at the ma ximum alc attack time rate , regardless of the mode and attack rate settings, until the adc output level has been reduced below the emergency limit threshold. this limits adc clipping if there is a sudden increase in the input signal level. 3.10.1 alc normal mode example using alc hold time feature input signals with different characteristics (e.g., voice vs. music) may require different settings for this parameter for optim um performance. increasing the alc hold time prevents the alc from reacting too quickly to brief periods of silence such as those that may appear in music recordings; having a shorter hold time, may be useful in voice applications where a faster reaction time helps to adjust the volume setting for speakers with different volumes. the waveform below shows the operation of the alch ld parameter. figure 8 : alc hold delay change 3.11 noise gate (normal mode only) a noise gate threshold prevents alc amplification of noise when there is no input signa l, or no signal above an expected background noise level. the noise gate is enabled by setting register 35, bit 3 (ngen), high, and the threshold level is set in register 35, bits 0 to 2 (ngth). this does not remove noise from the signal; when there is n o signal or a very quiet signal (pause) composed mostly of noise, the alc holds the gain constant instead of amplifying the signal towards the target threshold. the NAU8822A accomplishes this by comparing the input signal level against the noise gate thre shold. the noise gate only operates in conjunction with the alc and only in normal mode. the noise gate is asserted when: equation 1 : (signal at adc C pga gain C mic boost gain) < ngth (noise gate threshold level) h o l d d e l a y c h a n g e p g a g a i n p g a i n p u t p g a o u t p u t 1 6 m s d e l a y f o r a l c h t = 0 1 0 0 www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 23 of 89 j anuary 25 , 20 11 empoweraudio ? figure 9 : alc operation without noise gate figure 10 : noise gate operation p g a i n p u t p g a o u t p u t p g a g a i n p g a i n p u t p g a o u t p u t p g a g a i n n o i s e g a t e t h r e s h o l d www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 24 of 89 j anuary 25 , 20 11 empoweraudio ? 3.12 alc example with alc min/max limits and noise gate operation the drawing below shows the effects of alc ope ration over the full scale signal range. the drawing is color coded to be more clear as follows: blue original input signal (linear line from zero to maximum) green pga gain value over time (inverse to signal in target range) red output signal (held to a constant value in target range) figure 11 : alc response envelope 3.12.1 alc register map overview alc can be enabled for either or both the left and right adc channels. all alc functions and mode setting s are common to the left and right channels. when either the right or left pga is disabled, the respective pga will remain at the most recent gain value as set by the alc. registers that control the alc features and functions are: r32 enable left/right alc functions; set maximum gain, minimum gain r33 alc hold time, alc target signal level r34 alc limiter mode selection, attack parameters, decay parameters r35 enable noise gate, noise gate parameters r70 selection of signal level averaging options and al c table options r70 realtime readout of left channel gain value in use by alc (same as left in stereo operation) r71 realtime readout of right channel gain value in use by alc (same as right in stereo operation) r76 realtime readout of input signal level f rom averaging peak - to - peak input signal detector r77 realtime readout of input signal level from averaging input signal peak detector the following table shows some of the alc parameter values and their ranges. the complete list of settings and values is included in the detailed register map. a l c o p e r a t i o n r a n g e t a r g e t a l c s l - 6 d b g a i n ( a t t e n u a t i o n ) c l i p p e d a t a l c m n g a i n - 1 2 d b o u t p u t l e v e l - 3 9 d b - 3 9 d b - 6 d b + 6 d b - 1 2 d b 0 d b + 3 3 d b i n p u t l e v e l i n p u t < n o i s e g a t e t h r e s h o l d p g a g a i n r e g i s t e r b i t s n a m e v a l u e d e s c r i p t i o n 3 2 3 3 3 2 3 5 3 5 3 2 3 - 5 0 - 2 7 - 8 3 0 - 2 0 - 3 a l c s e l a l c m a x g a i n a l c m i n g a i n a l c l v l n g e n n g t h 1 1 1 1 1 0 0 0 1 0 1 1 1 0 0 0 a l c e n a b l e d b o t h c h a n n e l s n o i s e g a t e e n a b l e d n o i s e g a t e @ - 3 9 d b m a x a l c g a i n @ 3 5 . 2 5 d b m i n a l c g a i n @ - 1 2 d b t a r g e t a l c g a i n @ - 6 d b f s www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 25 of 89 j anuary 25 , 20 11 empoweraudio ? parameter register bits name default programmable range setting value minimum gain of pga 32 0 - 2 alcming ain 000 - 12db range: - 12db to +30db @ 6db increments maximum gain of pga 32 3 - 5 alcmaxg ain 111 35.25 db range: - 6.75db to +35.25db @ 6db increments alc function 32 7 - 8 alcen 00 disabled 00 = disable 01 = enable right channel 10 = enable left channel 11 = enable both channels alc target level 33 0 - 3 alclvl 1011 - 6dbfs range: - 2 2 .5db to - 1.5 dbfs @ 1.5db i ncrements alc hold time 33 4 - 7 alchld 0000 0ms range: 0ms to 1 024m s at 1010 and above (time s are for 0.75db steps, and double with every step) alc attack time 34 0 - 3 alcatk 0010 500 s alcm=0 - range: 1 25 s to 1 28 ms alcm=1 - range: 31 s to 32ms (time s are for 0.75db steps, and double with every step) alc decay time 34 4 - 7 alcdcy 0011 4 ms alcm = 0 - range: 500 s to 512 ms alcm = 1 - range: 125 s to 128 ms (time s are for 0.75db steps, and double with every step) limiter function 34 8 alcmode 0 disabled 0 = alc mode 1 = limiter mode table 5 : registers associated with alc and limiter control 3.13 limiter mode when register 34, bit 8, is high and alc is enabled in reg ister 32, bits 7 - 8 (alcen), the alc block operates in limiter mode. in this mode, the pga gain is constrained to be less than or equal to the pga gain setting when the limiter mode is enabled. in addition, attack and decay times are faster in limiter mod e than in normal mode as indicated by the different lookup tables for these parameters for limiter mode. the following waveform illustrates the behavior of the alc in limiter mode in response to changes in various alc parameters. figure 12 : alc limiter mode operation l i m i t e r e n a b l e d p g a g a i n p g a i n p u t p g a o u t p u t www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 26 of 89 j anuary 25 , 20 11 empoweraudio ? 4 adc digital block the adc digital block performs 24 - bit analog - to - digital conversion and signal processing , making available a high quality audio sample str eam the audio path digital interface . this block consists of a sigma - delta modul ator, digital decimator/ filter, 5 - band graphic equalizer, 3d effects, high pass filter, and a notch filter. the equalizer and 3d audio function block is a single resource th at may be used by either the adc or dac, but not both at the same time. the adc coding scheme is in twos complement format and the full - scale input level is proportional to vdda . with a 3.3v supply voltage, the full - scale level is 1.0v rms . registers th at affect the adc operation are: r2 power management enable/disable left/right adc r5 digital passthrough of adc output data into dac input r7 sample rate indication bits (affect filter frequency scaling) r14 oversampling, polarity inversion , and filter co ntrols for left/right adc r14 adc high pass filter audio mode or application mode selection r15 left channel adc digital volume control and update bit function r16 right channel adc digital volume control and update bit function 4.1 sampling / o versampling r at e , polarity control , digital passthrough the audio sample rate of the adc is determined entirely by the imclk internal master clock frequency, which is 128 times the base audio sample rate. a technique known as oversampling is used to improve noise and d istortion performance of the adc, but this does not affect the final audio sample rate. the default oversampling rate of the adc is 64x (64 times the audio sample rate), but this can be changed to 128x for greatly improved audio performance. the higher r ate increases power consumption by only approximately three milliwatts per channel, so for most applications, the improved quality is a good choice. there is almost zero increased power to also run the dacs at 128x oversampling, and the best overall quali ty will be achieved when both the dacs and adcs are operated at the same oversampling rate. the polarity of either adc output signal can be changed independently on either adc logic output as a feature sometimes useful in management of the audio phase. th is feature can help minimize any audio processing that may be otherwise required as the data are passed to other stages in the system. digital audio p assthrough allows the output of the adcs to be directly sent to the dacs as the input signal to the dac fo r dac output. in this mode of operation, the output data from the adcs are still available on the adcout logic pin. however, any external input signal for the dac will be ignored. the passthrough function is useful for many test and application purposes , and the dac output may be utilized in any way that is normally supported for the dac analog output signals. a d c d i g i t a l a u d i o i n t e r f a c e a d c d i g i t a l f i l t e r s d i g i t a l f i l t e r g a i n 5 - b a n d e q u a l i z e r h i g h p a s s f i l t e r n o t c h f i l t e r www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 27 of 89 j anuary 25 , 20 11 empoweraudio ? 4.2 adc digital volume control and update bit functionality the effective output audio volume of each adc can be changed using the digital volume co ntrol feature. this processes the output of the adc to scale the output by the amount indicated in the volume register setting. included is a digital mute value which will completely mute the signal output of the adc. the digital volume setting can ra nge from 0db through - 127db in 0.5db steps. i mportant : the r15 and r16 update bits are write - only bits. the primary intended purpose of the update bit is to enable simultaneous changes to both the left and right adc volume values, even though these value s must be written sequentially. when there is a write operation to either r15 or r16 volume settings, but the update bit is not set (value = 0), the new volume setting is stored as pending for the future, but does not go into effect. when there is a writ e operation to either r15 or r16 and the update bit is set (value = 1), then the new value in the register being written is immediately put into effect, and any pending value in the other adc volume register is put into effect at the same time. 4.3 adc program mable high pass filter each adc is optionally supported by a high pass filter in the digital output path. f ilter operation and settings are always the same for both left and right channels. the high pass filter has two differen t operating modes . in the audio mode, the filter is a simple first order dc blocking filter , with a cut - off frequency of 3 .7hz. in the application specific mode, the filter is a second order audio frequency filter , with a programmable cut - off frequency . the cutoff frequency of th e high pass filter is scaled depending on the sampling frequency indicated to the sys tem by the setting in register 7 . registers that affect operation of the programmable high pass filter are: r7 sample rate indication to the system (affects filter coeff icient internal scaling) r14 high - pass enable/disable, operating mode, and cut - off frequency the following table provides the exact cutoff frequenc ies with different sample rates as indicated to the system by means of register 7. the table shows the assum ed actual numerical sample rates as determined by the system clocks. detailed response curves are provided in the appendix section of this document. register 14, bits 4 to 6 (hpf) sample rate in khz (fs) r7(smplr) = 101 or 100 r7(smplr) = 011 or 010 r7 (smplr) = 001 or 000 8 11.025 12 16 22.05 24 32 44.1 48 000 82 113 122 82 113 122 82 113 122 001 102 141 153 102 141 153 102 141 153 010 131 180 156 131 180 156 131 180 156 011 163 225 245 163 225 245 163 225 245 100 204 281 306 204 281 306 204 281 306 101 261 360 392 261 360 392 261 360 392 110 327 450 490 327 450 490 327 450 490 111 408 563 612 408 563 612 408 563 612 table 6 : high pass fil ter cut - off frequencies in hz ( with hpfam register 14, bit 7 = 1) 4.4 programmable no tch filter each adc is optionally supported by a notch filter in the digital output path. filter operation and settings are always the same for both left and right channels. a notch filter is useful to a very narrow band of audio frequencies in a stop ban d around a given center frequency. the notch filter is enabled by setting register 27, bit 7 (nfcen), to 1. the center frequency is programmed by setting registers 27, 28, 29, and 30, bits 0 to 6 (nfa0[13:7], nfa0[6:0], nfa1[13:7], nfa1[6:0]), with twos compliment coefficient values calculated using table __. registers that affect operation of the notch filter are: www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 28 of 89 j anuary 25 , 20 11 empoweraudio ? r27 notch filter enable/disable r27 notch filter a0 coefficient high order bits and update bit r28 notch filter a0 coefficient low order bi ts and update bit r29 notch filter a1 coefficient high order bits and update bit r30 notch filter a1 coefficient low order bits and update bit i mportant : the register update bits are write - only bits. the update bit function is important so that all filte r coefficients actively being used are changed simultaneously , even though these register values must be written sequentially. when there is a write operation to any of the filter coefficient settings, but the update bit is not set (value = 0) , the value is stored as pending for the future, but does not go into effect. when there is a write operation to any coefficient register, and the update bit is set (value = 1), then the new value in the register being written is immediately put int o effect, and any pending coefficient value is put into effect at the same time. coefficient values are in the form of 2s - complement integer values, and must be calculated based upon the desired filter properties. the mathematical operations for calculating these coeffici ents are detailed in the following table . a 0 a 1 notation register value (dec) f c = center frequency (hz) f b = - 3db bandwidth (hz) f s = sample frequency (hz) nfca0 = - a 0 x 2 13 nfca1 = - a 1 x 2 12 note: values are rounded to the nearest whole number and convert ed to 2s compl ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? s b s b f f f f 2 2 tan 1 2 2 tan 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? s c f f x a ? 2 1 0 cos www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 29 of 89 j anuary 25 , 20 11 empoweraudio ? 5 dac digital block the dac digital block uses 24 - bit signal processin g to generate analog audio with a 16 - bit digital sample stream input. this block consists of a sigma - delta modul ator, digital decimator/ filter, and optional 5 - band graphic equalizer/ 3d effects block, and a dynamic range compressor/limiter . the dac coding scheme is in twos complement format and the full - scale output level is proportional to vdda . with a 3.3v supply voltage, the full - scale output level is 1.0v rms . registers that affect the dac operation are: r3 power management enable/disable left/right da c r5 digital passthrough of adc output data into dac input r7 sample rate indication bits (affect filter frequency scaling) r10 softmute, automute, oversampling options, polarity controls for left/right dac r11 left channel dac digital volume value; update bit feature r12 right channel dac digital volume value; update bit feature 5.1 dac soft mute both dacs are initialized with the softmute function disabled , which is a shared single control bit. softmute automatically ramps the dac digital volume down to zero volume when enabled, and automatically ramps the dac digital volume up to the register specified volume level for each dac when disabled. this feature provides a tool that is useful for using the dacs without introducing pop and click sounds. 5.2 dac automut e the analog output of both dacs can be automatically muted in a no signal condition. both dacs share a single control bit for this function. when automute is enabled, the analog output of the dac will be muted any time there are 1024 consecutive audio s amp le values with a zero value. if at any time there is a non - zero sample value, the dac will be un - muted, and the 1024 count will be reinitialized to zero. 5.3 dac sampling / oversampling rate, polarity control, digital passthrough the sampling rate of the d ac is determined entirely by the frequency of its input clock and the oversampling rate setting. the oversampling rate of the dac can be changed to 128x for improved audio performance at slightly higher power consumption. because the additional supply cu rrent is only 1ma, in most applications the 128x oversampling is preferred for maximum audio performance. the polarity of either dac output signal can be changed independently on either dac analog output as a feature sometimes useful in management of the a udio phase. this feature can help minimize any audio processing that may be otherwise required as the data are passed to other stages in the system. digital audio passthrough allows the output of the adcs to be directly sent to the dacs as the input signa l to the dac for dac output. in this mode of operation, the external digital audio signal for the dac will be ignored. the d a c d i g i t a l f i l t e r s d i g i t a l a u d i o i n t e r f a c e d a c d i g i t a l p e a k l i m i t e r 5 - b a n d e q u a l i z e r d i g i t a l g a i n 3 d d i g i t a l f i l t e r www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 30 of 89 j anuary 25 , 20 11 empoweraudio ? passthrough function is useful for many test and application purposes, and the dac output may be utilized in any way that is normal ly supported for the dac analog output signals. 5.4 dac digital volume control and update bit functionality the effective output audio volume of each dac can be changed using the digital volume control feature. this processes the output of the dac to scale t he output by the amount indicated in the volume register setting. included is a digital mute value which will completely mute the signal output of the dac. the digital volume setting can range from 0db through - 127db in 0.5db steps. important : the r11 and r12 update bits are write - only bits. the primary intended purpose of the update bit is to enable simultaneous changes to both the left and right dac volume values, even though these values must be written sequentially. when there is a write operatio n to either r11 or r12 volume settings, but the update bit is not set (value = 0), the new volume setting is stored as pending for the future, but does not go into effect. when there is a write operation to either r11 or r12 and the update bit is set (val ue = 1), then the new value in the register being written is immediately put into effect, and any pending value in the other dac volume register is put into effect at the same time. 5.5 dac automatic output peak limiter / volume boost both dacs are supported b y a digital output volume limiter/boost feature which can be useful to keep output levels within a desired range without any host/processor intervention. settings are shared by both dac channels. registers that manage the peak limiter and volume boost fun ctionality are: r24 limiter enable/disable, limiter attack rate, boost decay rate r25 limiter upper limit, limiter boost value the operation of the peak limiter is shown in the following figure. the upper signal graphs show the time varying level of the i nput and output signals , and the lower graph shows the gain characteristic of the limiter. when the signal level exceeds the limiter threshold value by 0.5db or greater, the dac digital signal level will be attenuated at a rate set by the limiter attack r ate value. when the input signal level is less than the boost lower limit by 0.5db or greater, the dac digital volume will be increased at a rate set by the boost decay rate value. the default boost gain value is limited not to exceed 0db (zero attenuati on). figure 13 : dac digital limiter control the limiter may optionally be set to automatically boost the dac digital signal level when the signal is more than 0.5db below the limiter threshold. this can be useful in applications in which it is desirable to compress the signal dynamic range. this is accomplished by setting the limiter boost register bits to a value greater than zero. if the limiter is disabled, this boost value will be applied to the dac digital output signal separate from other gain affecting values. d a c i n p u t s i g n a l e n v e l o p e d a c o u t p u t s i g n a l e n v e l o p e d i g i t a l g a i n 0 d b - 1 d b - 0 . 5 d b t h r e s h o l d - 1 d b www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 31 of 89 j anuary 25 , 20 11 empoweraudio ? 5.6 5 - band equalizer the NAU8822A includes a 5 - band graphic equalizer with low distortion, low noise, and wide dynamic range. the equalizer is applied to both left and right channels. the equalizer is grouped with the 3d stereo enhancement signal processing function. both functions may be assigned to support either the adc path, or the dac path, but not both paths simultaneously. registers that affect operation of the 5 - band equalizer are : r18 assign equalizer to dac path or to adc path (default = adc path) r18 band 1 gain control and cut - off frequency r19 band 2 gain control, center cut - off frequency, and bandwidth r20 band 3 gain control, center cut - off frequency, and bandwidth r21 band 4 gain control, center cut - off frequency, and bandwidth r22 band 5 gain control and cut - off frequency ea ch of the five equalizer bands is independently adjustable for maximum system f lexibility, and each offers up to 12db of boost and 12db of cut with 1db resolution. the high and the low bands are shelving filters (high - pass and low - pass, respectively), and the middle three bands are peak ing filters. details of the register value settings are described below. response curve examples are provided in the appendix of this document. register value equalizer band 1 (high pass) 2 (band pass) 3 (band pass) 4 (band pass) 5 (low pass) register 18 register 19 register 20 register 21 register 22 bits 5 & 6 bits 5 & 6 bits 5 & 6 bits 5 & 6 bits 5 & 6 eq1cf eq2cf eq3cf eq4cf eq5cf 00 80hz 230hz 650hz 1.8khz 5.3khz 01 105hz 300hz 850hz 2.4khz 6.9khz 10 135hz 385hz 1.1khz 3.2khz 9.0khz 11 175hz 500hz 1.4khz 4.1khz 11.7khz table 8 : equalizer center/cutoff frequencies register value gain registers binary hex 000 00 00h +12db bits 0 to 4 in registers 18 (eq1gc) 19 (eq2gc) 20 (eq3gc) 21 (eq4gc) 22 (eq5gc) 00001 01h +11db 00010 02h +10db - - - - - increments 1db per step 01100 0ch 0db 01101 17h - 11db - - - - - increments 1 db per step 11000 18h - 12db 11001 to 11111 19h to 1fh reserved table 9 : equalizer gains www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 32 of 89 j anuary 25 , 20 11 empoweraudio ? 5.7 3d stereo enhancement NAU8822A includes digital circuitry to provide flexible 3d enhancement to increase the perceived separation betwe en the right and left channels, and has multiple options for optimum acoustic performance. the equalizer is grouped with the 3d stereo enhancement signal processing function. both functions may be assigned to support either the adc path, or the dac path, but not both paths simultaneously. registers that affect operation of 3d stereo enhancement are: r18 assign equalizer to dac path or to adc path (default = adc path) r41 3d audio depth enhancement setting the amount of 3d enhancement applied can be progra mmed from the default 0% (no 3d effect) to 100% in register 41, bits 0 to 3 (depth3d), as shown in table __. note: 3d enhancement uses increased gain to achieve its effect, so that the source signal may need to be attenuated by up to 6db to avoid clippin g. register 41 bits 0 to 3 3ddepth 3d effect 0000 0% 0001 6.7% db 0010 13.4% db - - - increments 6.67% for each binary step in the input word 1110 93.3% 1111 100% table 10 : 3 d enhancement depth 5.8 companding companding is used i n digital communication systems to optimize signal - to - noise ratios with reduced data bit rates, using non - linear algorithms. NAU8822A supports the two main telecommunications companding standards on both the transmit and the receive sides: a - law and - law . the a - law algorithm is primarily used in european communication systems and the - law algorithm is primarily used by north america, japan, and australia. . companding converts 13 bits ( - law) or 12 bits (a - law) to 8 bits using non - linear quantization. the companded signal is an 8 bit word containing sign (1 - bit), exponent (3 - bits) and mantissa (4 - bits) f ollowing are the data compression equations set in the itu - t g.711 standard and implemented in the NAU8822A : 5.9 - law f(x) = ln( 1 + |x|) / ln( 1 + ) - 1 x 1 with =255 for the u.s. and japan 5.10 a - law f(x) = a|x| / ( 1 + lna) ????????????????????for x 1/a f(x) = ( 1 + lna|x|) / (1 + lna) ????????for 1/a x 1 with a=87.6 for europe the register affecting companding operation is: r5 enable 8 - bit mode, enable dac companding, enable adc companding www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 33 of 89 j anuary 25 , 20 11 empoweraudio ? the companded signal is an 8 - bit word consisting of a sign bit, three bits for the exponent, and four bits for the mantissa. when companding is enabled, the pcm interface must be set to an 8 - bit wo rd length. when in 8 - bit mode, the register 4 word length control (wlen) is ignored. companding mode register 5 bit 4 bit3 bit 2 bit 1 no companding (default ) 0 0 0 0 adc a - law 5.11 8 - bit word length writing a 1 to register 5, bit 5 (cmb8), will cause the pcm interface to use 8 - bit word length for data trans fer , overriding the word length configuration setting in wlen (register 4, bits 5 and 6.) . www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 34 of 89 j anuary 25 , 20 11 empoweraudio ? 6 a nalog outputs the NAU8822A features six different analog outputs. these are highly flexible and may be used individually or in pairs for many purposes. however , they are grouped in pairs and named for their most commonly used stereo application end uses . the following sections detail key features and functions of each type of output . included is a description of the associated output mixers. these mixers are separate internal functional blocks that are important t oward understanding all aspects of the analog output section. 6.1 m ain mixers (lmain mix and rmain mix ) each left and right channel is supported by an independent main mixer. this mixer combines signals from a various available signal sources i nternal to the device. each mixer may also be selectively enabled/disabled as part of the power management features . the outputs of these mixers are the only signal source for the headphone outputs, and the primar y signal source for the loudspeaker outputs. each mixer can accept either or both the left and right digital to analog (dac) outputs. normally, the left and right dac is mixed into the associated left and right main output mix. this additional capability to mix opposite dac channels enables switching the left and right dac outputs to the opposite channel, or mixing together the left and right dac signals C all without any processor or host intervention and processing overhead. each mixer also can also com bine signals directly from the respective left or right aux input, and from the output of the respective adc mix/boost stage output. each of these paths may be muted, or have an applied selectable gain between - 15db and +6db in 3db steps. registers that a ffect operation of the main mixers are: r3 power control for the left and right main mixer r49 left and right dac cross - mixing source selection options r50 left dac to left main mixer source selection option r51 right dac to right main mixer source select ion option r50 left aux and adc mix/boost source select, and gain settings r51 right aux and adc mix/boost source select, and gain settings 6.2 a uxiliary mixers (aux 1 mixer and aux2 mixer) each auxiliary analog output channel is supported by an independent mix er dedicated to the auxiliary output function. this mixer combines signals from a various available signal sources internal to the device. each mixer may also be selectively enabled/disabled as part of the power management features. unlike the main mixer s, the auxiliary mixers are not identical and combine different signal sets internal to the device. these mixers in conjunction with the auxiliary outputs greatly increase the overall capabilities and flexibility of the NAU8822A . the aux1 mixer combines t ogether any or all of the following: left main mixer output right main mixer output left dac output right dac output right adc mix/boost stage output the aux2 mixer combines together any or all of the following: left main mixer output left dac output left adc mix/boost stage output inverted output from aux1 mixer stage www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 35 of 89 j anuary 25 , 20 11 empoweraudio ? registers that affect operation of the auxiliary mixers are: r1 power control for the left and right auxiliary mixer r56 signal source selection for the aux2 mixer r57 signal source selecti on for the aux1 mixer 6.3 r ight speaker submixer the right speaker submixer serves two important functions. one is to optionally invert the output from the right main mixer as an optional signal source for the right channel loudspeaker output driver . this in version is normal and necessary in typical applications using the loudspeaker drivers. the other function of the right speaker submixer is to mix the rauxin input signal directly into the right channel speaker output driver. this enables the rauxin signal to be output on the right loudspeaker channel, but not be mixed to any other output. the traditional purpose of this path is to support an old - style beep sound, such as traditionally generated by a microprocessor output toggle bit. on the NAU8822A , this traditional function is supported by a full quality signal path that may be used for any purpose. the volume for this path has a selectable gain from - 15db through +6db in 3db step increments. there is no separate power management control feature for the right speaker submixer. the register that affects the right speaker submixer is: r43 input mute controls, volume for rauxin path 6.4 h eadphone outputs ( lhp and rhp ) these are high quality, high current output drivers intended for driving low imped ance loads such as headphones , but also suitable for a wide range of audio output applications . the only signal source for each of these outputs is from the associated left and right main mixer. power for this section is provided from the vdda pin. each driver may be selectively enabled/disabled as part of the power management features. each output can be individually muted, or controlled over a gain range of - 57db through +6db in 3db steps. gain changes for the two headphone outputs can be coordinated through use of an update bit feature as part of the register controls. additionally, clicks that could result from gain changes can be suppressed using an optional zero crossing feature. registers that affect the headphone outputs are: r2 power management control fo r the left and right headphone amplifier r52 volume, mute, update, and zero crossing controls for left headphone driver r53 volume, mute, update, and zero crossing controls for right headphone driver i mportant : the r52 and r53 update bits are write - only b its. the primary intended purpose of the update bit is to enable simultaneous changes to both the left and right headphone output volume values, even though these two register values must be written sequentially. when there is a write operation to either r52 or r53 volume settings, but the update bit is not set (value = 0), the new volume setting is stored as pending for the future, but does not go into effect. when there is a write operation to either r52 or r53 and the update bit is set (value = 1), th en the new value in the register being written is immediately put into effect, and any pending value in the other headphone output volume register is put into effect at the same time. zero - crossing controls are implemented to suppress clicking sounds that may occur when volume setting changes take place while an audio input signal is active. when the zero crossing function is enabled (logic = 1), any volume change for the affected channel will not take place until the audio input signal passes through the zero point in its peak - to - peak swing. this prevents any instantaneous voltage change to the audio signal caused by volume setting changes. if the zero crossing function is disabled (logic = 0), volume changes take place instantly on condition of the upda te bit, but without regard to the instantaneous voltage level of the affected audio input signal. www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 36 of 89 j anuary 25 , 20 11 empoweraudio ? 6.5 s peaker outputs these are high current outputs suitable for driving low impedance loads , such as an 8 - ohm loudspeaker. both outputs may be used separately f or a wide range of applications, however, the intended application is to use both outputs together in a btl (bridge - tied - load, and also, balanced - transformer - less) configuration. in most applications, this con figuration requires an additional signal inve rsion, which is a feature supported in the right speaker submixer block. this inversion is normal and necessary when the two speaker outputs are used together in a btl (bridge - tied - load, and also, balanced - transformer - less) configuration. in this physical configuration, the rspkout signal is connected to one pole of the loudspeaker, and the lspkout signal is connected to the other pole of the loudspeaker. mathematically, this creates within the loudspeaker a signal equal to (left - right). the desired math ematical operation for a stereo signal is to drive the speaker with (left+right). this is accomplished by implementing an additional inversion to the r ight channel signal. for most applications, best performance will be achieved when care is taken to ins ure that all gain and filter settings in both the left and right channel paths to the loudspeaker drivers are identical. power for the loudspeaker outputs is supplied via the vddspk pin, and ground is independently provided as the vsspk pin. this power op tion enables an operating voltage as high as 5vdc and helps in a system design to prevent high current outputs from creating noise on other supply voltage rails or system grounds. vsspk must be connected at some point in the system to vssa, but provision of the vsspk as a separate high current ground pin facili t ates managing the flow of current to prevent ground bounce and other ground noise related problems. each loudspeaker output may be selectively enabled/disabled as part of the power management feat ures. registers that affect the loudspeaker outputs are: r3 power management control of lspkout and rspkout driver outputs r3 speaker bias control (biasgen) set logic = 1 for maximum power and vddspk > 3.60vdc r 48 driver d istortion mode control r49 disabl e boost control for speaker outputs for vddspk 3.3v or lower r54 volume (gain), mute, update bit, and zero crossing control for left speaker driver r55 volume (gain), mute, update bit, and zero crossing control for right speaker driver i mportant : the r49 boost control option is set in the power - on reset condition for high voltage operation of vddspk. if vddspk is greater than 3. 6 vdc, the r49 boost control bits should be remain at the power - on default settings. this insures reliable operation of the part, proper dc biasing, and optimum scaling of the signal to enable the output to achieve full scale output when vddspk is greater than vdda. in the boost mode, the gain of the output stage is increased by a factor of 1.5 times the normal gain value. i mportan t : the r54 and r55 update bits are write - only bits. the primary intended purpose of the update bit is to enable simultaneous changes to both the left and right headphone output volume values, even though these two register values must be written sequenti ally. when there is a write operation to either r54 or r55 volume settings, but the update bit is not set (value = 0), the new volume setting is stored as pending for the future, but does not go into effect. when there is a write operation to either r54 or r55 and the update bit is set (value = 1), then the new value in the register being written is immediately put into effect, and any pending value in the other headphone output volume register is put into effect at the same time. zero - crossing controls a re implemented to suppress clicking sounds that may occur when volume setting changes take place while an audio input signal is active. when the zero crossing function is enabled (logic = 1), any volume change for the affected channel will not take place until the audio input signal passes through the zero point in its peak - to - peak swing. this prevents any instantaneous voltage change to the audio signal caused by volume setting changes. if the zero crossing function is disabled (logic = 0), volume chang es take place instantly on condition of the update bit, but without regard to the instantaneous voltage level of the affected audio input signal. the loudspeaker drivers may optionally be operated in an ultralow distortion mode. this mode may require addi tional external passive components to insure stable operation in some system configurations. no external components are required in normal mode speaker driver operation. distortion performance in normal operation is excellent, and already suitable for al most every application. www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 37 of 89 j anuary 25 , 20 11 empoweraudio ? 6.6 a uxiliary outputs these are high current outputs suitable for driving low impedance loads such as headphones or line level loads. power for these outputs is supplied via the vddspk pin, and ground is also independently provided as the vsspk pin. this power option e nables an operating voltage as high as 5vdc and helps in a system design to prevent high current outputs from creating noise on other supply voltage rails or system grounds. vsspk must be connected at some point in the system to vssa, but provision of the vsspk as a separate high current ground pin facilitates managing the flow of current to prevent ground bounce and other ground noise related problems. each auxiliary output driver may be selectively enabled/disabled a s part of the power management features . registers that affect the auxiliary outputs are: r3 power management control of auxout1 and auxout2 outputs r3 speaker bias control (biasgen) set logic = 1 for maximum power and vddspk > 3.60vdc r49 disable boost c ontrol for au xout1 and auxout2 for vddspk 3.3vdc or lower r56 mute, gain control, and input selection controls for auxout2 r57 mute, gain control, and input selection controls for auxout1 i mportant : the r49 boost control option is set in the power - on rese t condition for high voltage operation of vddspk. if vddspk is greater than 3. 6 vdc, the r49 boost control bits should be remain at the power - on default settings. this insures reliable operation of the part, proper dc biasing, and optimum scaling of the s ignal to enable the output to achieve full scale output when vddspk is greater than vdda. in the boost mode, the gain of the output stage is increased by a factor of 1.5 times the normal gain value. an optional alternative function for these outputs is to provide a virtual ground for an external headphone device. this is for eliminating output capacitors for the headphone amplifier circuit in applications where this type of design is appropriate. in this type of application, the auxout output is typicall y operated in the muted condition. in the muted condition , and with the output configured in the non - boost mode (also requiring that vddspk < 3.61vdc) , the auxout output dc level will rem ain at the internal vref level. th is the same internal dc level as used by the headphone outputs. because these dc levels are nominally the same, dc current flowing through the headphone in this mode of operation is minimized. depending on the application, one or both of the auxiliary outputs may be used in this fashion . 7 m iscellaneous functions 7.1 s low timer clock an internal slow timer clock is supplied to automatically control features that happen over a relatively periods of time, or time - spans . this enables the NAU8822A to implement long time - span features without any host/processor management or intervention. two features are supported by the slow timer clock . these are an optional automatic time out for the zero - crossing holdoff of pga volume cha nge s , and timing for debouncing of the mechanical jack detection feature . if e ither feature is required, the slow timer clock must be enabled. the slow timer clock is initialized in the disabled state. the slow timer clock is controlled by only the following register : r7 sample rate indication select, and slow timer clock e nable the slow timer clock rate is derived from mclk using an integer divider that is compensated for the sample rate as indicated by the r7 sample rate register. if the sample rate register value precisely matches the actual sample rate, then the intern al slow timer clock rate will be a constant value of 128ms. if the actual sample rate is , for example, 44.1 k hz and the sample rate selected in r7 is 48 k hz, the rate of the slow timer clock will be approximately 10% slower in direct proportion of the actua l vs. indicated sample rate. this scale of difference should not be important in relation to the dedicated end uses of the slow timer clock . www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 38 of 89 j anuary 25 , 20 11 empoweraudio ? 7.2 g eneral purpos e inputs and outputs (gpio1, gpio2, gpio3) and j ack d etection three pins are provided in the nau882 2a that may be used for limited logic input/output functions. gpio1 has multiple possible functions, and may be either a logic input or logic output. gpio2 and gpio3 may be either line level analog inputs, or logic inputs dedicated to the purpose of jack detection. gpio2 and gpio3 do not have any logic output capability or function. only one gpio can be selected for jack detection. if a gpio is selected for the jack detection feature, the slow timer clock must be enabled. the jack detection function is automatically debounced such that momentary changes to the logic value of this input pin are ignored. the slow timer clock is necessary for the debouncing feature. registers that control the gpio functionality are: r8 gpio functional selection options r9 jack detection feature input selection and functional options if a gpio is selected for the jack detection function, the required slow timer clock determines the duration of the time windows for the input logic debouncing function. because the logic le vel changes happen asynchronously to the slow timer clock , there is inherently some variability in the timing for the jack detection function. a continuous and persistent logic change on the gpio pin used for jack detection will result in a valid internal output signal within 2.5 to 3.5 periods of the slow timer clock . any logic change of shorter duration will be ignored. the threshold voltage for a jack detection logic - low level is no higher than 1.0vdc. the threshold voltage for a jack detection logic - high level is no lower than 1.7vdc. these levels will be reduced as the vddc core logic voltage pin is reduced below 1.9vdc. if the rlin or llin input pin is used for the gpio function, the analog signal path should be configured to be disconnected from i ts respective pga input. this will not cause harm to the device, but could cause unwanted noise introduced through the pga path. 7.3 a utomated features linked to jack detection some functionality can be automatically controlled by the jack detection logic. t his feature can be used to enable the internal analog amplif i er bias voltage generator , and /or enable analog output drivers automatically as a result of detecting a logic change at a gpio pin assigned to the purpose of jack detection. this eliminates any requirement for the host/processor to perform these functions. the internal analog amplifier bias generator creates the vref voltage reference and bias voltage used by the analog amplifiers. the ability to control it is a power management feature. this i s implemented as a logical or function of either the debounced internal jack detection signal, or the abiasen control bit in register 1. the bias generator will be powered if either of these control signals is enabled (value = 1). power management contr ol of four different outputs is also optionally and selectively subject to control linked with the jack detection signal. the four outputs that c an be controlled this way are the headphone driver signal pair, loudspeaker driver signal pair, auxout1, and a uxout2. register settings determine which outputs may be enabled, and whether they are enabled by a logic 1 or logic 0 value. output control is a logical and operation of the jack detection controls, and of the register control bits that normally contr ol the outputs. both controls must be in the on condition for a given output to be enabled. registers that affect these functions are: r9 gpio pin selection for jack detect function, jack detection enable, vref jack enable r13 bit mapped selection of w hich outputs are to be enabled when jack detect is in a logic 1 state r13 bit mapped selection of which outputs are to be enabled when jack detect is in a logic 0 state www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 39 of 89 j anuary 25 , 20 11 empoweraudio ? 8 clock selection and generation the NAU8822A has two basic clock modes that support the adc and dac data converters. i t can accept external clocks in the slave mode, o r in the master mode, it can generate the required clocks from an external reference frequency using an internal pll (phase locked loop). the internal pll is a fractional typ e scaling pll, and therefore, a very wide range of external reference frequencies can be used to create accurate audio sample rates. separate from this adc and dac clock subsystem, audio data are clocked to and from the NAU8822A by means of the control log ic described in the digital audio interfaces section. the audio bit rate and audio sample rate for this data flow are managed by the frame sync (fs) and bit clock (bclk) pins in the digital audio interface. it is important to understand that the sampling rate for the adc and dac data converters is not determined by the digital audio interface, and instead, this rate is derived exclusively from the internal master clock (imclk). i t is therefore a requirement that the digital audio interface and data conve rters be ope rated synchronously , and that the fs , bclk, and imclk signals are all derived from a common reference frequency . if these three clocks signals are not synchronous, audio quality will be reduced. the imclk is always exactly 256 times the sampli n g rate of the data converters. imclk is output from the master clock prescaler. the prescaler reduces by an integer division factor the input frequency input clock. the source of this input frequency clock is either the external mclk pin, or the output from the internal pll block. registers that are used to manage and control the clock subsystem are: r1 power management, enable control for pll (default = disabled) r6 master/slave mode, clock scaling, clock selection r7 sample rate indication (scales dsp coefficients and timing C does not affect actual sample rate r8 mux control and division factor for pll output on gpio1 r36 pll prescaler, integer portion of pll frequency multiplier r37 highest order bits of 24 - bit fraction of pll frequency multiplier r 38 middle order bits of 24 - bit fraction of pll frequency multiplier r39 lowest order bits of 24 - bit fraction of pll frequency multiplier in master mode, the imclk signal is used to generate fs and bclk signals that are driven onto the fs and bclk pins and input to the digital audio interface. fs is always imclk/256 and the duty cycle of fs is automatically adjusted to be correct for the mode selected in the digital audio interface. the frequency of bclk may optionally be divided to optimize the bit clock rate for the application scenario. in slave mode, there is no connection between imclk and the fs and bclk pins. in this mode, fs and blck are strictly input pins, and it is the responsibility of the system designer to insure that fs, bclk, a nd imclk are synchronous and scaled appropriately for the application. www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 40 of 89 j anuary 25 , 20 11 empoweraudio ? figure 14 : pll and clock select circuit 8.1 phase locked loop (pll) general description the pll may be optionally used to multiply an external inp ut clock reference frequency by a high resolution fractional number. to enable the use of the widest possible range of external reference clocks, the pll block includes an optional divide - by - two prescaler for the input clock, a fixed divide - by - four scaler on the pll output, and an additional programmable integer divider that is the master clock prescaler. the high resolution fraction for the pll is the ratio of the desired pll oscillator frequency (f 2 ), a nd the reference frequency at the pll input (f 1 ). t his can be represented as r = f 2 /f 1 , with r in the form of a decimal number: xy.abcde fgh . to program the NAU8822A , this value is separated into an integer portion (xy), and a fractional portion , abcdefgh . the fractional p ortion of the multiplier is a value that when represented as a 24 - bit binary number (stored in three 9 - bit registers on the NAU8822A ), very closely matches the exact desired multiplier factor. to keep the pll within its optimal operating range, the integer portion of the decimal num ber (xy), must be any of the following decimal values: 6, 7, 8, 9, 10, 11, or 12. the input and output dividers outside of the pll are often helpful to scale frequencies as needed to keep the xy value within the required range. also, the optimum pll oscillator frequency is in the range between 90mhz and 100mhz, and thus, it is best to keep f 2 withi n this range. in summary , for any given design, choose : ? imclk = desired master clock = (256)*(desired codec sample rate) ? f 2 = (4)*(p)(imclk) , where p is th e master clock prescale integer value ; optimal f 2 : 90mhz< f 2 <100mhz ? f 1 = (mclk)*(d), where d is the pll p rescale factor of 1, or 2 , and mclk is the frequency at the mclk pin note: the integer values for d and p are chosen to keep the pll in its optima l operating range. it may be best to assign initial values of 1 to both d and p, and then by inspection , determine if they should be a different value . ? r = f 2 /f 1 = xy.abcdefgh decimal value , which is the fractional frequency multiplication factor for the pll ? n = xy truncated integer portion of the r value , and limited to decimal value 6, 7, 8, 9, 10, 11, or 12 ? k = (2 24 ) * (0.abcdefgh), rounded to the nearest whole integer value, then converted to a binary 24 - bit value ? r36 is set with the whole number integ er portion , n, of the multiplier ? r37, r38, r39 are set collectively with the 24 - bit binary fractional portion , k, of the multiplier ? r36 pll prescaler set as necessary ? r6 master clock prescaler and bclk output scaler set as necessary m c l k f / 2 p l l f 2 = r ( f 1 ) f / 4 f 2 f p l l c s b / g p i o 1 p l l t o g p i o 1 o u t p u t s c a l e r r 8 [ 5 , 4 ] p l l p r e s c a l e r r 3 6 [ 4 ] m a s t e r c l o c k p r e s c a l e r r 6 [ 7 , 6 , 5 ] g p i o 1 m u x c o n t r o l r 8 [ 2 , 1 , 0 ] f s b c l k i m c l k = 2 5 6 f s p l l b l o c k m a s t e r c l o c k s e l e c t r 6 [ 8 ] f / 2 5 6 f / n d i g i t a l a u d i o i n t e r f a c e m a s t e r / s l a v e s e l e c t r 6 [ 0 ] a d c d a c f 1 f / n b c l k o u t p u t s c a l e r r 6 [ 4 , 3 , 2 ] 0 1 0 1 0 1 f / n www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 41 of 89 j anuary 25 , 20 11 empoweraudio ? 8.1.1 phase locked loop (pll) design example in an example application, a desired sample rate for the dac is known to be 48.000 k hz. therefore, it is also known that the imclk rate will be 256fs, or 12.288mhz. because there is a fixed divide - by - four scaler on the pll output, then the desired pll oscillator output frequency will be 49.152mhz. in this example system design, there is already an available 12.000mhz clock from the usb subystem . to reduce system cost, this clock will also be used for audio. therefore, to use the 12mhz clo ck for audio, the desired fractional multiplier ratio would be r = 49.152/12.000 = 4.096. this value, however, does not meet the requirement that the xy whole number portion of the multiplier be in the inclusive range between 6 and 12. to meet the requ irement, the master clock prescaler can be set for an additional divide - by - two factor. this now makes the pll required oscillator frequency 98.304 mhz, and the improved multiplier value is now r = 98.304/12.000 = 8.192. to complete this portion of the des ign example , the integer portion of the multiplier is truncated to the value, 8. the fractional portion is multiplied by 2 24 , as to create the needed 24 - bit binary fraction al value . the calculation for this is: (2 24 )(0.192) = 3221225 .472. it is best to round this value to the nearest whole value of 3221225, or hexadecimal 0x3126e9. t hus, the values to be programmed to set the pll multiplier whole number integer and fraction are: r 36 0xnm8 ; integer portion of fraction, (nm represents other settings i n r36) r37 0x00c ; highest order 6 - bits of 24 - bit fraction r38 0x093 ; middle 9 - bits of 24 - bit fraction r39 0x0e9 ; lowest order 9 - bits of 24 - bit fraction below are additional examples of results for this calculation applied to commonly available clock frequencies and desired imclk 256fs sample rates. mclk (mhz) desired 256fs imclk rate (mhz) pll oscillator f 2 (mhz) pll prescaler divide r master clock divide r fractional multiplier r = f 2 /f 1 integer portion n (hex) fractional portion k (hex) 12.0 11.28960 90.3168 1 2 7.526400 7 86c226 12.0 12.28800 98.3040 1 2 8.192000 8 3126e9 14.4 11.28960 90.3168 1 2 6.272000 6 45a1ca 14.4 12.28800 98.3040 1 2 6.826667 6 d3a06d 19.2 11.28960 90.3168 2 2 9.408000 9 6872b0 19.2 12.28800 98.3040 2 2 10.240000 a 3d70a3 19.8 11.28960 90.3168 2 2 9.122909 9 1f76f8 19.8 12.28800 98.3040 2 2 9.929697 9 ee009e 24.0 11.28960 90.3168 2 2 7.526400 7 86c226 24.0 12.28800 98.3040 2 2 8.192000 8 3126e9 26.0 11.28960 90.3168 2 2 6.947446 6 f28bd4 26.0 12.28800 98.3040 2 2 7.5 61846 7 8fd526 table 12 : pll frequency examples 8.2 csb/gpio1 as pll output csb/gpio1 is a multi - function pin that may be used for a variety of purposes. if not required for some other purpose, this pin may be configured to output th e clock frequency from the pll subsystem. this is the same frequency that is available from the pll subsystem as the input to the master clock prescaler. this frequency may be optionally divided by an additional integer f actor of 2, 3, or 4 , before being output on gpio1. www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 42 of 89 j anuary 25 , 20 11 empoweraudio ? 9 c ontrol interfaces 9.1 selection of control mode the NAU8822A features include a serial control bus that provides access to all of the device control registers. this bus may be configured either as a 2 - wire interface that is interoperable w ith industry standard implementations of the i2c serial bus, or as a 3 - wire/4 - wire bus compatible with commonly used industry implementations of the spi (serial peripheral interface) bus. mode selection is accomplished by means of combination of the mode c ontrol logic pin, and the spien control bit in register 7 or register 73 . the following table shows the three functionally different modes that are supported. mode pin spien bit r7[8] spien bit r73[8] description 0 0 0 2 - wire interface, read/write operat ion 1 x dont care x dont care x dont care as by utilizing general purpose i/o pins on the host controller and software bit banging techniques to create the required timing. the option to set spi 4 - wire mode using r73[8] eliminates the requirement to chang e the mode pin state back to logic zero in order to begin 4 - wire spi operation. note that if r73[8] is set while in 2 - wire mode, that spi mode becomes enforced and that there will be no way to reverse this change in 2 - wire mode. 9.2 2 - w ire - serial control mode (i 2 c style interface) the 2 - wire bus is a bidirectional serial bus protocol. this protocol defines any device that sends data onto the bus as a transmitter (or master), and the receiving device as the receiver (or slave). the NAU8822A can function only as a slave device when in the 2 - wire interface configuration. 9.3 2 - wire protocol convention all 2 - wire interface operations must begin with a start condition, which is a high - to - low transition of sdio while sclk is high. all 2 - wire interface operations are t erminated by a stop condition, which is a low to high transition of sdio while sclk is high. a stop condition at the end of a read or write operation places the device in a standby mode. an acknowledge (ack), is a software convention is used to indicate a successful data transfer. to allow for the ack response, the transmitting device releases the sdio bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sdio line low to acknowledge the reception of the eight bits of d ata. following a start condition, the master must output a device address byte. this consists of a 7 - bit device address, and the lsb of the device address byte is the r/w (read/write) control bit. when r/w=1, this indicates the master is initiating a r ead operation from the slave device, and when r/w=0, the master is initiating a write operation to the slave device. if the device address matches the address of the slave device, the slave will output an ack during the period when the master allows for t he ack signal. www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 43 of 89 j anuary 25 , 20 11 empoweraudio ? figure 15 : valid start condition figure 16 : valid acknowledge figure 17 : v alid stop condition figure 18 : slave address byte, control address byte, and data byte 9.4 2 - w ire write operation a write operation consists of a two - byte instruction followed by one or more data bytes. a write operation requires a start condition, followed by a valid device address byte with r/w=0, a valid control address byte, data byte(s), and a stop condition. the NAU8822A is permanently programmed with 0011010 as the device address. if the device address matches this value, the NAU8822A will respond with the expected ack signaling as it accepts the data being transmitted into it. figure 19 : byte write sequence s c l k s d i o s t a r t s c l k s d i o r e c e i v e s d i o t r a n s m i t a c k 9 t h c l o c k s t o p s c l k s d i o device address byte control address byte data byte 0 0 1 1 0 1 0 r / w a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 0 0 0 0 0 1 d e v i c e a d d r e s s = 3 4 h c o n t r o l r e g i s t e r a d d r e s s 9 - b i t d a t a b y t e s d i o s c l k a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 8 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 1 1 a c k a c k s t a r t s t o p a c k www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 44 of 89 j anuary 25 , 20 11 empoweraudio ? 9.5 2 - wire read operation a read op eration consists of a three - byte write instruction followed by a read instruction of one or more data bytes. the bus master initiates the operation issuing the following sequence: a start condition, device address byte with the r/w bit set to 0, and a control register address byte. this indicates to the slave device which of its control registers is to be accessed. the NAU8822A is permanently programmed with 0011010 as its device address. if the device address matches this value, the NAU8822A will r espond with the expected ack signaling as it accepts the control register address being transmitted into it. after this, the master transmits a second start condition, and a second instantiation of the same device address, but now with r/w=1. after again recognizing its device address, the NAU8822A transmits an ack, followed by a two byte value containing the nine bits of data from the selected control register inside the NAU8822A . unused bits in the byte containing the msb information from the NAU8822A a re output by the NAU8822A as zeros. during this phase, the master generates the ack signaling with each byte transferred from the NAU8822A . if there is no stop signal from the master, the NAU8822A will internally auto - increment the target control register address and then output the two data bytes for this next register in the sequence. this process will continue as long as the master continues to issue ack signaling. if the control register address being indexed inside the NAU8822A reaches the value 0x7f (hexadecimal) and the value for this register is output, the index will roll over to 0x00. the data bytes will continue to be output until the master terminates the read operation by issuing a stop condition. figure 20 : read sequence 9.6 spi control interface modes the serial peripheral interface (spi) is a widely utilized interface protocol, and the NAU8822A supports two modes of spi operation. when the mode pin on the NAU8822A is in a logic high cond ition, the device operates in the spi 3 - wire write mode. this is a write - only mode with a 16 - bit transaction size. if the mode pin is in a logic low condition, and the spien control bit is set in register 5, the spi 4 - wire read/write modes are enabled. 0 0 0 0 0 1 d e v i c e a d d r e s s = 3 4 h c o n t r o l r e g i s t e r a d d r e s s 2 n d d e v i c e a d d r e s s = 3 5 h s c l k a 6 a 5 a 4 a 3 a 2 a 1 a 0 0 0 0 0 0 0 0 d 8 0 1 1 a c k s t a r t s t o p a c k 1 6 - b i t d a t a 0 1 1 0 1 0 1 0 a c k s t a r t d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 a c k a c k www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 45 of 89 j anuary 25 , 20 11 empoweraudio ? 9.7 spi 3 - wire write operation whenever the mode pin on the NAU8822A is in the logic high condition, the device control interface will operate in the 3 - wire write mode. this is a write - only mode that does not require the fourth wire normally used to read data from a device on an spi bus implementation. this mode is a 16 - bit transaction consisting of a 7 - bit control register address, and 9 - bits of control register data. in this mode, sdio data bits are clocked continuously into a temporary holding register on each rising edge of sclk, until the csb pin undergoes a low - to - high logic transition. at the time of the transition, the most recent 16 - bits of data are latched into the NAU8822A , with the 9 - bit data value being written into the NAU8822A control register addressed by the control register address portion of the 16 - bit value. figure 21 : register write operation using a 16 - bit spi interface 9.8 spi 4 - wire 24 - bit write and 32 - bit read operation the spi 4 - wi re read/write modes are enabled when the NAU8822A mode pin is in a logic low condition, and when the spi enable bit (spien) is set in register 7, bit 8. note that any time after either a hardware reset or software reset of the NAU8822A has occurred, the s pien bit must be set before the spi 4 - wire read/write modes can be used. this must be done using either the spi 3 - wire write mode, or using the 2 - wire write operation. 9.9 spi 4 - wire write operation the spi 4 - wire write operation is a full spi data transact ion. however, only three wires are needed, as this is a write - only operation with no return data. a fourth wire is needed only when there are bi - directional data. the csb/gpio1 pin on the NAU8822A is used as the chip select function in the spi transacti on. after csb is held in a logic low condition, data bits from sdio are clocked into the NAU8822A on every rising edge of sclk. a write operation is indicated by the value 0x10 (hexadecimal) placed in the device address byte of the transaction. this byte is followed by a 7 - bit control register address and a 9 - bit data value packed into the next two bytes of three - byte sequence. after the lsb of the data byte is clocked into the NAU8822A , the 9 - bit data value is automatically transferred into the NAU8822A register addressed by the control register address value. if only a single register is to be written, csb/gpio must be put into a logic high condition after the lsb of the data byte is clocked into the device. if csb/gpio1 remains in a logic low conditio n, the NAU8822A will auto - index the control register address value to the next higher address, and the next two bytes will be clocked into the next sequential NAU8822A register address. this will continue as long as csb/gpio1 is in the logic low condition . if the control register address being indexed inside the NAU8822A reaches the value 0x7f (hexadecimal), and after the value for this register is written, the index will roll over to 0x00 and the process will continue. c o n t r o l r e g i s t e r a d d r e s s 9 - b i t d a t a b y t e s d i o s c l k c s b / g p i o 1 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 8 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 46 of 89 j anuary 25 , 20 11 empoweraudio ? figur e 22 : register write operation using a 24 - bit spi interface 9.10 spi 4 - wire read operation the spi 4 - wire read operation is a full spi data transaction with a two - byte address phase, and two - byte data phase. the csb/gpio1 pin on the n au8822a is used as the chip select function in the spi transaction. after csb is held in a logic low condition, data bits from sdio are clocked into the NAU8822A on every rising edge of sclk. a read operation is indicated by the value 0x20 (hexadecimal) p laced in the device address byte of the transaction. this byte is followed by a 7 - bit control register address, padded by a non - used zero value in the lsb portion of the control register address. after the lsb of the control register address is clocked, the NAU8822A will begin outputting its data on the gpio3 pin, beginning with the very next sclk rising edge. these data are transmitted in two bytes and contain the 9 - bit value from the NAU8822A register selected by the control register address. the dat a are transmitted msb first, with the first 7 - bits of the two byte value padded by zeros. if only a single register is to be read, csb/gpio must be put into a logic high condition after the lsb of the data byte 1 is clocked from the NAU8822A . if csb/gpio 1 remains in a logic low condition, the NAU8822A will auto - index the control register address value to the next higher address, and the next two bytes will be clocked from the next sequential NAU8822A register address. this will continue as long as csb/gp io1 is in the logic low condition. if the control register address being indexed inside the NAU8822A reaches the value 0x7f (hexadecimal), and after the value for this register is output, the index will roll over to 0x00 and the process will continue. figure 23 : register read operation through a 32 - bit spi interface 9.11 software reset the entire NAU8822A and all of its control registers can be reset to default initial conditions by writing any value to re gister 0, using any of the control interface modes. writing to any other valid register address terminates the reset condition, but all registers will now be set to their power - on default values. 0 0 0 0 0 0 0 1 d e v i c e a d d r e s s = 1 0 h c o n t r o l r e g i s t e r a d d r e s s 9 - b i t d a t a b y t e s d i o s c l k c s b / g p i o 1 a 6 a 5 a 4 a 3 a 2 a 1 a 0 d 8 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 c s b / g p i o 1 0 0 1 0 0 0 0 0 d e v i c e a d d r e s s = 2 0 h c o n t r o l r e g i s t e r a d d r e s s s d i o s c l k 0 0 0 0 0 0 d a t a b y t e 2 s o d a t a b y t e 1 a 5 a 4 a 3 a 2 a 1 a 0 d 8 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 a 6 0 0 www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 47 of 89 j anuary 25 , 20 11 empoweraudio ? 10 digital audio interfaces the NAU8822A can be configured a s either the master or the slave, by setting register 6, bit 0, to 1 for master mode and to 0 for slave mode . slave mode is the default if this bit is not written. in master mode, NAU8822A outputs both frame sync (fs) and the audio data bit clock (bclk,) has full control of the data transfer. in the s lave mode, an external controller supplies bclk and fs . data are latched o n the rising edge of bclk ; adcout clock s out adc data, while dacin clocks in data for the dacs . when not transmitting data, adcout pull s low in the default state . depending on the application, the output can be configured to pull up or pull down. to configure the output to pull up, write a 1 to register 60, bit 3 (pudps) . when the time slot function is enabled (see below), there a re additional output state modes including controlled tri - state capability. NAU8822A supports six audio formats as shown in table __ , all with an msb - first data format . the default mode is i 2 s. pcm mode register 4, bits 3 - 4 aiff register 4, bit 7 lrp reg ister 60, bit 8 pcmtsen right justified 00 0 0 left justified 01 0 0 i 2 s 10 0 0 pcm a 11 0 0 pcm b 11 1 0 pcm time slot 11 dont care 10.1 right - justified a udio d ata in right - justified mo de, the lsb is clocked on the last bclk rising edge before fs transitions. when fs is high, left channel data is transmitted and when fs is low, right channel data is transmitted. this is shown in the figure below. figure 24 : right - justified audio interface 10.2 left - justified a udio d ata in left - justified mode , the msb is clocked on the first bclk rising edge after fs transitions. when fs is high, left channel data is transmitted and when fs is low, righ t channel dat a is transmitted. this is shown in the figure below . l e f t c h a n n e l r i g h t c h a n n e l f s n - 1 n 1 2 m s b l s b d a c i n / a d c o u t b c l k n - 1 n 1 2 m s b l s b www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 48 of 89 j anuary 25 , 20 11 empoweraudio ? figure 25 : left - justified audio interface 10.3 i 2 s a udio d ata in i 2 s mode , the msb is clocked on the second bclk rising edge after fs tran sitions. when fs is low, left channel data is transmitted and when fs is high, right channel dat a is transmitted. this is shown in the figure below . figure 26 : i2s audio interface 10.4 pcm a a udio d ata i n the pcm a mode, left channel data is transmitted first followed immediately by right channel data. the left channel msb is clocked on the second bclk rising edge after the fs pulse rising edge, and the right channel msb is clocked on the next sclk after the left channel lsb. this is shown in the figure below . l e f t c h a n n e l r i g h t c h a n n e l f s n - 1 n 1 2 m s b l s b b c l k n - 1 n 1 2 m s b l s b l e f t c h a n n e l r i g h t c h a n n e l f s n - 1 n 1 2 m s b l s b d a c i n / a d c o u t b c l k 1 b c l k n - 1 n 1 2 m s b l s b www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 49 of 89 j anuary 25 , 20 11 empoweraudio ? figure 27 : pcm a audio interface 10.5 pcm b a udio d ata in the pcm b mode, left channel data is transmitted first followed immediately by right cha nnel data. the left channel msb is clocked on the first bclk rising edge after the fs pulse rising edge, and the right channel msb is clocked on the next sclk after the l eft channel lsb. this is shown in the figure below . fi gure 28 : pcm - b audio interface 10.6 pcm time slot a udio d ata the pcm time slot mode is used to delay the time at which the dac and/or adc data are clocked. this increases the flexibility of the NAU8822A to be used in a wide range of s ystem designs. one key application of this feature is to enable multiple NAU8822A or other devices to share the audio data bus, thus enabling more than two channels of audio. this feature may also be used to swap left and right channel data, or to cause both the left and right channels to use the same data. normally, the dac and adc data are clocked immediately after the frame sync (fs). in the pcm time slot mode, the audio data are delayed by a delay count specified in the device control registers. th e left channel msb is clocked on the bclk rising edge defined by the delay count set in registers 59 and 60. the right channel msb is clocked on the bclk rising edge defined by the delay count set in registers 60 and 61. register 60 also controls adcout output impedance options enabling the adcout pin to share the same signal wire with other drivers. the default is the non - shared mode, with the output enable bit (puden) set to logic=1. this results in the adcout pin being actively driven at all times (n ever in a high - impedance state). l e f t c h a n n e l f s n - 1 n 1 2 m s b l s b d a c i n / a d c o u t b c l k 1 b c l k w o r d l e n g t h , w l e n [ 6 : 5 ] r i g h t c h a n n e l n - 1 n 1 2 l s b l e f t c h a n n e l f s n - 1 n 1 2 m s b l s b d a c i n / a d c o u t b c l k 1 b c l k w o r d l e n g t h , w l e n [ 6 : 5 ] r i g h t c h a n n e l n - 1 n 1 2 m s b l s b www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 50 of 89 j anuary 25 , 20 11 empoweraudio ? however, if puden is logic=0, and pudpe (pull - up/down enable) is logic=1, then adcout will be pulled high or low by means of an internal passive resistor. this enables wired - or type bus sharing. the choice of passive pull - up, or passive pull - down is determined by the pudps (pull - up/down select) bit. if puden and pudpe are both logic=0, adcout is high impedance, except when actively transmitting left and right channel audio data. after outputting audio channel data, adcout will return to high impedance on the bclk negative edge during the lsb data period if register 60, bit 7 (tri), is high, or on the bclk positive edge of lsb if register 60, bit 7 (tri), is low. tri - stating on the negative edge allows the transmission of data by multiple sources in adjacent timeslots with reduced risk of bus driver contention. figure 29 : pcm time slot audio interface l e f t c h a n n e l r i g h t c h a n n e l f s n - 1 n - 2 n 1 2 3 n - 1 n - 2 n 1 2 3 m s b l s b m s b l s b d a c i n / a d c o u t b c l k www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 51 of 89 j anuary 25 , 20 11 empoweraudio ? 10.7 con trol interface timing figure 30 : 3 - wire control m ode t iming figure 31 : 4 - wire control m ode t iming t r i s e t f a l l c s b s c l k s d i o t s c k t s c k h t s c k l t s c c s h t s d i o s t s d i o h t c s b h t c s b l t r i s e t f a l l c s b s d i o g p i o 3 t s c k t s c k h t s c k l t c s s c s t s c c s h t s d i o s t s d i o h t g 3 d t c s b h t g 3 z d t z g 3 d www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 52 of 89 j anuary 25 , 20 11 empoweraudio ? symbol description min typ max unit t sck sclk cycle time 80 - - ns t sckh sclk high pulse width 35 - - ns t sckl sclk low pulse width 35 - - ns t rise rise time for all control interface signals - - 10 ns t fall fall time for all control interface signals - - 10 ns t csscs csb falling edge to 1 st sclk falling edge setup time (4 wire mode only) 30 - - ns t sccs h last sclk rising edge to csb rising edge hold time 30 - - ns t csbl csb low time 30 - - ns t csbh csb high time between csb lows 30 - - ns t sdios sdio to sclk rising edge setup time 20 - - ns t sdioh sclk rising edge to sdio hold time 20 - - ns t zg3d delay time from csb falling edge to gpio3 active (4 wire mode only) -- -- 15 ns t g3zd delay time from csb rising edge to gpio3 tri - state (4 - wire mode only) -- -- 15 ns t g3d delay time from sclk falling edge to gpio3 (4 - wire mode only) - - 15 ns table 15 : three - and four wire control timing parameters figure 32 : two - wire control m ode t iming symbol description min typ max unit t stah sclk falling edge to sdio falling edge hold timing in start / repeat start condition 600 - - ns t stas sdio rising edge to sclk falling edge setup timing in repeat start condition 600 - - ns t stos sdio rising edge to sclk rising edge setup timing in stop condition 600 - - ns t sckh sclk high p ulse width 600 - - ns t sckl sclk low pulse width 1,300 - - ns t rise rise time for all 2 - wire mode signals - - 300 ns t fall fall time for all 2 - wire mode signals - - 300 ns t sdios sdio to sclk rising edge data setup time 100 - - ns t sdioh sclk falling edge to sdio data hold time 0 - 600 ns table 16 : two - wire control timing parameters t s t a h t s t a h t s t o s t s t a s t s d i o s t s d i o h t s c k l t s c k h t r i s e t f a l l s c l k s d i o www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 53 of 89 j anuary 25 , 20 11 empoweraudio ? 10.8 audio interface timing: figure 33 : digital audio interface slave mode timing figure 34 : digital audio interface master mode timing symbol description min typ max unit t bck bc l k cycle time in slave mode 50 - - ns t bckh bc l k high pulse width in slave mode 20 - - ns t bckl bc l k low pulse width in slave mode 20 - - ns t fss fs to bc l k rising edge setup time in slave mode 20 - - ns t fsh bc l k rising edge to fs hold time in slave mode 20 - - ns t fsd bcl k f alling edge to fs delay time in master mode - - 10 ns t rise rise time for all audio in terface signals - - 10 ns t fall fall time for all audio interface signals - - 10 ns t dis adcin to bc l k rising edge setup time 15 - - ns t dih bc l k rising edge to adcin hold time 15 - - ns t dod bc l k f alling edge to dacout delay time - - 10 ns table 17 : audio interface timing parameters t f s h t f s s t f s h t f s s t d i s t d i h t d o d t b c k t b c k h t b c k l t r i s e t f a l l b c l k ( s l a v e ) f s ( s l a v e ) a d c i n d a c o u t t f s d t f s d t d i s t d i h t d o d b c l k ( m a s t e r ) f s ( m a s t e r ) a d c i n d a c o u t www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 54 of 89 j anuary 25 , 20 11 empoweraudio ? 11 application information 11.1 typical application schematic figure 35 : schematic with recommended external components for typical application with ac - coupled headphones and stereo electret (ecm) style microphones. note 1: all non - polar capacitors are assumed to be low esr type parts, such as with mlc construction or similar. if capacitors are not low esr, additional 0.1ufd and/or 0.01ufd capacitors may be necessary in parall el with the bulk 4.7ufd capacitors on the supply rails. note 2: load resistors to ground on outputs may be helpful in some applications to insure a dc path for the output capacitors to charge/discharge to the desired levels. if the output load is always p resent and the output load provides a suitable dc path to ground, then the additional load resistors may not be necessary. if needed, such load resistors are typically a high value, but a value dependent upon the application requirements. note 3: to minim ize pops and clicks, large polarized output capacitors should be a low leakage type. note 4: depending on the microphone device and pga gain settings, common mode rejection can be improved by choosing the resistors on each node of the microphone such that the impedance presented to any noise on either microphone wire is equal. note 5: unused analog input pins should be left as no - connection. note 6: unused digital input pins should be tied to ground. vdda rspkout c 4 4 . 7 uf c 3 4 . 7 uf c 2 4 . 7 uf c 1 4 . 7 uf vddspk vss c 12 1 uf 13 14 9 10 7 8 11 15 16 17 18 23 29 26 31 25 nau 8822 a v ddb v dda v ddc v ssd v ssa mclk adcout dacin bclk vref micbias rhp csb / gpio 1 sclk sdio lspkout rmicn rmicp mode fs v ddspk v ssspk vddc vddb vss c 9 4 . 7 uf c 10 4 . 7 uf c 8 220 uf rlin / gpio 3 llin / gpio 2 30 lhp c 7 220 uf analog inputs : no connection if not used ecm electret type mic c 14 1 uf c 13 1 uf lmicn lmicp c 16 1 uf c 15 1 uf lauxin rauxin r 1 2200 ohm r 4 0 ohm r 2 2200 ohm r 3 0 ohm ecm electret type mic r 5 220 k ohm vss vddb jack switch detection example vss sleeve on 3 . 5 mm audio connector right headphone ring on 3 . 5 mm stereo connector left headphone tip on 3 . 5 mm stereo connector + + auxout 1 auxout 2 c 5 1 uf c 6 1 uf optional vss optional vss 19 20 2 1 5 4 32 27 6 28 24 12 21 22 3 r 7 r 6 r 8 r 9 c 11 1 uf www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 55 of 89 j anuary 25 , 20 11 empoweraudio ? 11.2 recommended power up and power down sequences to minimi ze pop and click noise, the NAU8822A should be powered up and down using the procedure s in this section as guidance. the power - up procedure should be followed upon system power - up, or after any time that the NAU8822A has been issued a register reset comma nd . the strongest cause of pops and clicks in most system is the sudden charging or discharging of capacitors used for ac - coupling to inputs and outputs. any sudden change in voltage will cause a pop or click, with or without ac - coupling capacitors in the signal path. the general strategy for pop and click reduction is to allow such charging and discharging to happen slowly. 11.2.1 power up (and after a software generated register reset) procedure guidance turn on external power supplies and wait for supply volt ages to settle . this amount of time will be dependent on the system design. software may choose to test the NAU8822A to determine when it is no longer in an active reset condition. this procedure is described in more detail in the sections relating to p ower supplies. if the vddspk supply voltage is 3.60v or less, the next step should be to configure all of the output registers for low voltage operation. this sets the internal dc levels and gains to optimal levels for operation at lower voltages. regist er settings required for this are: r49 bit 2, spkbst; bit 3, aux2bst; bit 4, aux1bst, set to logic = 1 as a general policy, it is a good idea to put any input or output driver paths into the mute condition any time internal register and data path configu rations are being changed. be sure at this time that all used inputs and outputs are in their muted/disconnected condition. next, the internal dc tie - off voltage buffers should be enabled: r1 bit 2, iobufen, set to logic = 1 r1 bit 8, dcbufen, set to logi c = 1 if setting up for greater than 3.60v operation value to be written to r1 = 0x104 at this point, the NAU8822A has been prepared to start charging any input/output capacitors to their normal operating mode charge state. if this is done slowly, then th ere will be no pops and clicks. one way to accomplish this is to allow the internal/external reference voltage to charge slowly by means of its internal coupling resistors. this is accomplished by: r1 bits 1, bit 0, refimp set to 80 k setting r1 bit 2, a biasen, set to logic = 1 value to be written to r1 = 0x10d after this, the system should wait approximately 250ms, or longer , depending on the external components that have been selected for a given specific application. after this, outputs may be enabled, but with the drivers still in the mute condition. unless power management requires outputs to be turned off when not used, it is best for pops and clicks to leave outputs enabled at all times, and to use the output mute controls to silence the outputs as needed. next, the NAU8822A can be programmed as needed for a specific application. the final step in most applications will be to unmute any outputs, and then begin normal operation. 11.2.2 power down powering down is more application specific. the most impo rtant step is to mute all outputs before any other steps. it then may be further helpful to disable all outputs just before the system power - down sequence is started. www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 56 of 89 j anuary 25 , 20 11 empoweraudio ? 11.2.3 u nused input/output tie - off information in audio and voice systems, any time there is a sudden change in voltage to an audio signal, an audible pop or click sound may be the result. systems that change inputs and output configurations dynamically, or which are required to manage low power operation, need special attention to possible pop an d click situations. the NAU8822A includes many features which may be used to greatly reduce or eliminate pop and click sounds. the most common cause of a pop or click signal is a sudden change to an input or output voltage. this may happen in either a dc coupled system, or in an ac coupled system. the strategy to control pops and clicks is similar for either a dc coupled system, or an ac coupled system. the case of the ac coupled system is the most common and the more difficult situation, and therefore, the ac coupled case will the focus for this information section. when an input or output pin is being used, the dc level of that pin will be very close to ? of the vdda voltage that is present on the vref pin. the only exception is that when outputs are o perated in the 5 - volt mode known as the 1.5x boost condition, then the dc level for those outputs will be equal to 1.5xvref. in all cases, any input or output capacitors will become charged to the operating voltage of the used input or output pin. the goa l to reduce pops and clicks is to insure that the charge voltage on these capacitors does not change suddenly at any time. when an input or output is in a not - used operating condition, it is desirable to keep the dc voltage on that pin at the same voltage level as the dc level of the used operating condition. this is accomplished using special internal dc voltage sources that are at the required dc values. when an input or output is in the not - used condition, it is connected to the correct internal dc vol tage as not to have a pop or click. this type of connection is known as a tie - off condition. two internal dc voltage sources are provided for making tie - off connections. one dc level is equal to the vref voltage value, and the other dc level is equal t o 1.5x the vref value. all inputs are always tied off to the vref voltage value. outputs will automatically be tied to either the vref voltage value or to the 1.5xvref value, depending on the value of the boost control bit for that output. that is to say, when an output is set to the 1.5x gain condition, then that same output will automatically use the 1.5xvref value for tie - off in the not - used condition. to conserve power, these internal voltage buffers may be enabled/disabled using control register s ettings. to better manage pops and clicks, there is a choice of impedance of the tie - off connection for unused outputs. the nominal values for this choice are 1 k and 30 k . the low impedance value will better maintain the desired dc level in the case w hen there is some leakage on the output capacitor or some dc resistance to ground at the NAU8822A output pin. a tradeoff in using the low - impedance value is primarily that output capacitors could change more suddenly during power - on and power - off changes. automatic internal logic determines whether an input or output pin is in the used or un - used condition. this logic function is always active. an output is determined to be in the un - used condition when it is in the disabled unpowered condition, as deter mined by the power management registers. an input is determined to be in the un - used condition when all internal switches connected to that input are in the open condition. www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 57 of 89 j anuary 25 , 20 11 empoweraudio ? figure 36 : tie - off optio ns for input and output pin examples register controls that directly affect the tie - off features are: register 1 enable buffers for 1.0xvref tie - off register 1 enable buffer for 1.5xvref tie - off register 49 tie - off impedance selection register 74 i nput tie - off management and manual overrides register 75 input tie - off buffer controls and manual overrides register 79 output tie - off buffer controls and manual overrides note: resistor tie - off switches will open/close regardless of whether or not the associated internal dc buffer is in the enabled or disabled condition. 1 k 3 0 k 1 k 3 0 k 1 k 3 0 k 3 0 k 3 0 k 3 0 k v r e f a u x m i c l i n h p a u x o u t s p k o u t r a r b i o b u f e n r 1 [ 2 ] d c b u f e n r 1 [ 8 ] a o u t i m p r 4 9 [ 0 ] 1 . 5 x v r e f n o t s e l e c t e d l o g i c o u t p u t d i s a b l e d n o t s e l e c t e d l o g i c n o t s e l e c t e d l o g i c o u t p u t d i s a b l e d & 1 . 5 x b o o s t o u t p u t d i s a b l e d & - 1 . 0 x n o - b o o s t i o b u f e n r 1 [ 2 ] www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 58 of 89 j anuary 25 , 20 11 empoweraudio ? 11.3 power consumption the NAU8822A has flexible power management capability which allows sections not being used to be powered down, to draw minimum current in battery - powered applications . the following table shows typical power consumption in different operating conditions. the off condition is the initial power - on state with all subsystems powered down, and with no applied clocks. mode conditions vdda = 3v vddc = 1.8v vddb = 3v tota l power ma ma ma mw off 0.008 0.001 0.0003 0.025 sleep vref maintained @ 300 k, no clocks, k, no clocks, vref maintained @ 5k, no clocks, hp, 44.1khz, quiescent 16 hp, 44.1khz, quiescent 16 hp, 44.1khz, 0.6 vrms 16 hp, 44.1khz, www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 59 of 89 j anuary 25 , 20 11 empoweraudio ? 11.4 supply currents of specific blocks the NAU8822A can be programmed to enable / disable various analog blocks individually, and the current to some of t he major blocks can be reduced with minimum impact on performance. the table below shows the change in current consumed with different register settings. sample rate settings affect current consumption of vddc supply. lower sampling rates draw lower cur rent. register function bit vdda current increase/ decrease when enabled dec hex 1 01 power management 1 refimp[1:0] +100a for 80k and 300k +260a for 3k +100a +600a +540a +200a +200a +140a +300a +300a +650a +650a +800a +800a +250a +250a +225a +225a 600a with no snr decrease @ 8khz www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 60 of 89 j anuary 25 , 20 11 empoweraudio ? 12 appendix a : d igital filter characteristics p arameter c onditions m in t yp m ax u nits adc filter passband +/ - 0 .015db 0 0.454 f s - 6db 0.5 fs passband ripple +/ - 0.01 5 db stopband 0.546 fs stopband attenuation f > 0.546*fs - 60 db gro up delay 28.25 1/fs adc high pass filter high pass filter corner frequency - 3db 3.7 hz - 0.5db 10.4 hz - 0.1db 21.6 hz dac filter passband +/ - 0.035db 0 0.454 fs - 6db 0.5 fs passband ripple +/ - 0.035 db stopband 0.546 fs stopban d attenuation f > 0.546*fs - 55 db group delay 28 1/fs table 20 : digital filter char a cteristics terminology 1. stop band attenuation (db) C the degree to which the frequency spectrum is attenuated (outside audio band) 2. pas s - band ripple C any variation of the frequency response in the pass - band region 3. note that this delay applies only to the filters and does not include other latencies, such as from the serial data interface www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 61 of 89 j anuary 25 , 20 11 empoweraudio ? figure 37 : dac f ilter frequency response figure 38 : dac filter ripple figure 39 : adc filter frequency response figure 40 : adc filter ripple www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 62 of 89 j anuary 25 , 20 11 empoweraudio ? figure 41 : ad c highpass filter response, audio mode figure 42 : adc highpass filter response, hpf e nabled, fs = 48 k hz figure 43 : adc highpass filter response, hpf enabled, fs = 24 k hz figure 44 : adc highpass filter response, hpf enabled, fs = 12 k hz 10 20 30 hz d b r 0 - 2 - 4 - 6 100 300 500 hz 700 900 100 300 500 hz 700 900 d b r 0 - 80 - 20 - 40 - 60 d b r 0 - 80 - 20 - 40 - 60 100 300 500 hz 700 900 100 300 500 hz 700 900 d b r 0 - 80 - 20 - 40 - 60 d b r 0 - 80 - 20 - 40 - 60 100 300 500 hz 700 900 100 300 500 hz 700 900 d b r 0 - 80 - 20 - 40 - 60 d b r 0 - 80 - 20 - 40 - 60 www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 63 of 89 j anuary 25 , 20 11 empoweraudio ? figure 45 : eq band 1 gains for lowest cut - off frequency figure 46 : eq band 2 peak filter gains for lowest cut - off frequency with eq2bw = 0 figure 47 : eq band 2, eq2bw = 0 versus eq2bw = 1 figure 48 : eq band 3 peak filter gains for lowest cut - off frequency with eq3bw = 0 d b r +15 +5 0 - 5 - 10 - 15 +10 20 20k 50 100 200 500 1k 2k 5k 10k hz d b r +15 +5 0 - 5 - 10 - 15 +10 +15 +5 0 - 5 - 10 - 15 +10 20 20k 50 100 200 500 1k 2k 5k 10k hz 20 20k 50 100 200 500 1k 2k 5k 10k hz d b r +15 +5 0 - 5 - 10 - 15 +10 +15 +5 0 - 5 - 10 - 15 +10 20 20k 50 100 200 500 1k 2k 5k 10k hz 20 20k 50 100 200 500 1k 2k 5k 10k hz 20 20k 50 100 200 500 1k 2k 5k 10k hz 20 20k 50 100 200 500 1k 2k 5k 10k hz +15 +5 0 - 5 - 10 - 15 +10 d b r +15 +5 0 - 5 - 10 - 15 +10 +15 +5 0 - 5 - 10 - 15 +10 d b r +15 +5 0 - 5 - 10 - 15 +10 d b r +15 +5 0 - 5 - 10 - 15 +10 +15 +5 0 - 5 - 10 - 15 +10 d b r 20 20k 50 100 200 500 1k 2k 5k 10k hz 20 20k 50 100 200 500 1k 2k 5k 10k hz www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 64 of 89 j anuary 25 , 20 11 empoweraudio ? figure 49 : eq band 3, eq3bw = 0 versus eq3bw = 1 figure 50 : eq band 4 peak filter gains for lowest cut - off frequencies with eq4bw = 0 figure 51 : eq band 4, eq4bw = 0 versus eq4bw =1 figure 52 : eq band 5 gains fo r lowest cut - off frequency +15 +5 0 - 5 - 10 - 15 +10 d b r 20 20k 50 100 200 500 1k 2k 5k 10k hz +15 +5 0 - 5 - 10 - 15 +10 d b r +15 +5 0 - 5 - 10 - 15 +10 +15 +5 0 - 5 - 10 - 15 +10 d b r 20 20k 50 100 200 500 1k 2k 5k 10k hz 20 20k 50 100 200 500 1k 2k 5k 10k hz t +15 +5 0 - 5 - 10 - 15 +10 d b r t t +15 +5 0 - 5 - 10 - 15 +10 d b r +15 +5 0 - 5 - 10 - 15 +10 +15 +5 0 - 5 - 10 - 15 +10 d b r +15 +5 0 - 5 - 10 - 15 +10 d b r +15 +5 0 - 5 - 10 - 15 +10 +15 +5 0 - 5 - 10 - 15 +10 d b r 20 20k 50 100 200 500 1k 2k 5k 10k hz 20 20k 50 100 200 500 1k 2k 5k 10k hz +15 +5 0 - 5 - 10 - 15 +10 d b r 20 20k 50 100 200 500 1k 2k 5k 10k hz +15 +5 0 - 5 - 10 - 15 +10 d b r +15 +5 0 - 5 - 10 - 15 +10 +15 +5 0 - 5 - 10 - 15 +10 d b r 20 20k 50 100 200 500 1k 2k 5k 10k hz 20 20k 50 100 200 500 1k 2k 5k 10k hz www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 65 of 89 j anuary 25 , 20 11 empoweraudio ? 13 appendix b : companding tables 13.1 - law / a - law codes for zero and full scale level - law a - law sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) + full scal e 1 000 0000 1 010 1010 + zero 1 111 1111 1 101 0101 - zero 0 111 1111 0 101 0101 - full scale 0 000 0000 0 010 1010 table 21 : companding codes for zero and full - scale 13.2 - law / a - law output codes (digital mw) sample - law a - law sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) sign bit (d7) chord bits (d6,d5,d4) step bits (d3,d2,d1,d0) 1 0 001 1110 0 011 0100 2 0 000 1011 0 010 0001 3 0 000 1011 0 010 0001 4 0 001 1110 0 011 0100 5 1 001 1110 1 011 0100 6 1 000 1011 1 010 0001 7 1 000 1011 1 010 0001 8 1 001 1110 1 011 0100 table 22 : companding output codes www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 66 of 89 j anuary 25 , 20 11 empoweraudio ? 14 appendix c : details of register operation register function name bit description dec hex 8 7 6 5 4 3 2 1 0 0 00 software re set any write operation to this register resets all registers to default values 1 01 power management 1 dcbufen power control for internal tie - off buffer used in 1.5x boost conditions 0 = internal buffer unpowered 1 = enabled aux1m xen power control for aux1 mixer supporting auxout1 analog output 0 = unpowered 1 = enabled aux2mxen power control for aux2 mixer supporting auxout2 analog output 0 = unpowered 1 = enabled pllen power control for inte rnal pll 0 = unpowered 1 = enabled micbiasen power control for microphone bias buffer amplifier (micbias output, pin#32) 0 = unpowered and micbias pin in high - z condition 1 = enabled abiasen power control for internal analog b ias buffers 0 = unpowered 1 = enabled iobufen power control for internal tie - off buffer used in non - boost mode ( - 1.0x gain) conditions 0 = internal buffer unpowered 1 = enabled refimp select impedance of reference string used to establish vref for internal bias buffers 00 = off (input to internal bias buffer in high - z floating condition) 01 = 80 k nominal impedance at vref pin 10 = 300 k nominal impedance at vref pin 11 = 3 k nominal impedance at vref pin default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 2 02 power management 2 rhpen right headphone driver enable, rhp analog outpu t, pin#29 0 = rhp pin in high - z condition 1 = enabled lhpen left headphone driver enabled, lhp analog output pin#30 0 = lhp pin in high - z condition 1 = enabled sleep sleep enable 0 = device in normal operating mode 1 = devic e in low - power sleep condition rbsten right channel input mixer, radc mix/boost stage power control 0 = radc mix/boost stage off 1 = radc mix/boost stage on lbsten left channel input mixer, ladc mix/boost stage power control 0 = ladc mix/boost stage off 1 = ladc mix/boost stage on rpgaen right channel input programmable amplifier (pga) power control 0 = right pga input stage off 1 = enabled lpgaen left channel input programmable amplifier power contr ol 0 = left pga input stage off 1 = enabled radcen right channel analog - to - digital converter power control 0 = right adc stage off 1 = enabled ladcen left channel analog - to - digital converter power control 0 = left adc stage o ff 1 = enabled default >> 0 0 0 0 0 0 0 0 0 0x000 reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 67 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 3 03 power management 3 auxout1en auxout1 analog output power control, pin#21 0 = auxout1 output d river off 1 = enabled auxout2en auxout2 analog output power control, pin#22 0 = auxout2 output driver off 1 = enabled l spken lspkout left speaker driver power control, pin#25 0 = lspkout output driver off 1 = enabled r spk en rspkout left speaker driver power control, pin#23 0 = rspkout output driver off 1 = enabled reserved reserved rmixen right main mixer power control, rmain mixer internal stage 0 = rmain mixer stage off 1 = enabled lmixen left main mixer power control, lmain mixer internal stage 0 = lmain mixer stage off 1 = enabled rdacen right channel digital - to - analog converter, rdac, power control 0 = rdac stage off 1 = enabled ldacen le ft channel digital - to - analog converter, ldac, power control 0 = ldac stage off 1 = enabled default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 4 04 audio interface bclkp bit clock phase inversion option for bclk, pin#8 0 = normal phase 1 = input logic sense inverted lrp phase control for i2s audio data bus interface 0 = normal phase operation 1 = inverted phase operation pcma and pcmb left/right word order control 0 = msb is valid on 2 nd rising edge of bclk after rising edg e of fs 1 = msb is valid on 1 st rising edge of bclk after rising edge of fs wlen word length (24 - bits default) of audio data stream 00 = 16 - bit word length 01 = 20 - bit word length 10 = 24 - bit word length 11 = 32 - bit word length aifmt audio interface data format (default setting is i2s) 00 = right justified 01 = left justified 10 = standard i2s format 11 = pcma or pcmb audio data format option dacphs dac audio data left - right ordering 0 = left dac data in left phase of lrp 1 = left dac data in right phase of lrp (left - right reversed) adcphs adc audio data left - right ordering 0 = left adc data is output in left phase of lrp 1 = left adc data is output in right phase of lrp (left - right reversed) mono mono operation enable 0 = mono mode with audio data in left phase of lrp 1 = normal stereo mode of operation default >> 0 0 1 0 1 0 0 0 0 0x050 reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 68 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 5 05 companding reserved cmb8 8 - bit word enable for companding mode of operation 0 = normal operation (no companding) 1 = 8 - bit operation for companding mode daccm dac companding mode control 00 = off (normal linear operation) 01 = reserved 10 = u - law companding 11 = a - law companding adccm adc companding mode control 00 = off (normal linear operation) 01 = reserved 10 = u - law companding 11 = a - law companding addap dac audio data input option to route directly to adc data stream 0 = no passthrough, normal operation 1 = adc output data stream routed to dac input data path default >> 0 0 0 0 0 0 0 0 0 0x000 reset val ue 6 06 clock control 1 clkm master clock source selection control 0 = mclk, pin#11 used as master clock 1 = internal pll oscillator output used as master clock mclksel scaling of master clock source for internal 256fs rate ( divid e by 2 = default) 000 = divide by 1 001 = divide by 1.5 010 = divide by 2 011 = divide by 3 100 = divide by 4 101 = divide by 6 110 = divide by 8 111 = divide by 12 bclksel scaling of output frequency at bclk pin#8 when chip is in mast er mode 000 = divide by 1 001 = divide by 2 010 = divide by 4 011 = divide by 8 100 = divide by 16 101 = divide by 32 110 = reserved 111 = reserved reserved clkioen enables chip master mode to drive fs and bclk outputs 0 = fs and bclk are inputs 1 = fs and bclk are driven as outputs by internally generated clocks default >> 1 0 1 0 0 0 0 0 0 0x140 reset value 7 07 clock control 2 4wspien 4 - wire control interface enable reserved smplr audio data sample rate indication (48khz default). sets up scaling for internal filter coefficients, but does not affect in any way the actual device sample rate. should be set to value most closely matching the actual sample rate determined by 256fs internal node. 000 = 48 k hz 001 = 32 k hz 010 = 24 k hz 011 = 16 k hz 100 = 12 k hz 101 = 8 k hz 110 = reserved 111 = reserved sclken slow timer clock enable. starts internal timer clock derived by dividing master clock. 0 = disabled 1 = enabled default >> 0 0 0 0 0 0 0 0 0 0x000 reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 69 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 8 08 gpio reserved gpio1pll clock divisor applied to pll clock for output from a gpio pin 00 = divide by 1 01 = divide b y 2 10 = divide by 3 11 = divide by 4 gpio1pl gpio1 polarity inversion control 0 = normal logic sense of gpio signal 1 = inverted logic sense of gpio signal gpio1sel csb/gpio1 function select (input default) 000 = use as inpu t subject to mode pin#18 input logic level 001 = reserved 010 = temperature ok status output ( logic 0 = thermal shutdown) 011 = dac automute condition (logic 1 = one or both dacs automuted) 100 = output divided pll clock 101 = pll locked condition (l ogic 1 = pll locked) 110 = output set to logic 1 condition 111 = output set to logic 0 condition default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 9 09 jack detect 1 jckmiden automatically enable internal bias amplifiers on jack detection state as sensed through gpio pin associated to jack detection function bit 7 = logic 1: enable bias amplifiers on jack at logic 0 level bit 8 = logic 1: enable bias amplifiers on jack at logic 1 level jacden jack detection feature enable 0 = disabled 1 = enable jack detection associated functionality jckdio select jack detect pin (gpio1 default) 00 = gpio1 is used for jack detection feature 01 = gpio2 is used for jack detection feature 10 = gpio3 is used for jack detectio n feature 11 = reserved reserved default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 10 0a dac control reserved softmt softmute feature control for dacs 0 = disabled 1 = enabled reserved dacos dac oversampling rate selection (64x default) 0 = 64x oversampling 1 = 128x oversampling automt dac automute function enable 0 = disabled 1 = enabled rdacpl dac right channel output polarity control 0 = normal polari ty 1 = inverted polarity ldacpl dac left channel output polarity control 0 = normal polarity 1 = inverted polarity default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 11 0b left dac volume l dacvu dac volume update bit feature. write - only bit for synchronized l/r dac changes if logic = 0 on r11 write, new r11 value stored in temporary register if logic = 1 on r11 write, new r11 and pending r12 values become active ldacgain dac left digital volume control (0db def ault attenuation value). expressed as an attenuation value in 0.5db steps as follows: 0000 0000 = digital mute condition 0000 0001 = - 127.0db (highly attenuated) 0000 0010 = - 126.5db attenuation - all intermediate 0.5 step values through maximum C 1111 1110 = - 0.5db attenuation 1111 1111 = 0.0db attenuation (no attenuation) default >> 0 1 1 1 1 1 1 1 1 0x0ff reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 70 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 12 0c right dac volume r dacvu dac volume update bit feature. write - only bit for synchronized l/r dac changes if logic = 0 on r12 write, new r12 value stored in temporary register if logic = 1 on r12 write, new r12 and pending r11 values become active rdacgain dac right digital volume control (0db default attenuation va lue). expressed as an attenuation value in 0.5db steps as follows: 0000 0000 = digital mute condition 0000 0001 = - 127.0db (highly attenuated) 0000 0010 = - 126.5db attenuation - all intermediate 0.5 step values through maximum volume C 1111 1110 = - 0.5db attenuation 1111 1111 = 0.0db attenuation (no attenuation) default >> 0 1 1 1 1 1 1 1 1 0x0ff reset value 13 0d jack detect 2 reserved jckdoen1 outputs drivers that are automatically enabled whenever the designated jack detection input is in the logic = 1 condition, and the jack detection feature is enabled bit 4 = 1: enable left and right headphone output drivers bit 5 = 1: enable left and right speaker output drivers bit 6 = 1: enable auxout2 output driver bit 7 = 1: enable auxout1 output driver jckdoen0 outputs drivers that are automatically enabled whenever the designated jack detection input is in the logic = 0 condition, and the jack detection feature is enabled bit 0 = 1: enable left and right headphone output drivers bit 1 = 1: enable left and right speaker output drivers bit 2 = 1: enable auxout2 output driver bit 3 = 1: enable auxout1 output driver default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 14 0e adc control hpfen high pass filter enable control for filter of adc output data stream 0 = high pass filter disabled 1 = high pass filter enabled hpfam high pass filter mode selection 0 = normal audio mode, 1 st order 3.7hz high pass filter for dc blo cking 1 = application specific mode, variable 2 nd order high pass filter hpf application specific mode cutoff frequency selection < see text and table for details > adcos adc oversampling rate selection (64x default) 0 = 64x ove rsampling rate for reduced power 1 = 128x oversampling for better snr reserved radcpl adc right channel polarity control 0 = normal polarity 1 = sign of radc output is inverted from normal polarity ladcpl adc left channel polarity control 0 = normal polarity 1 = sign of ladc output is inverted from normal polarity default >> 1 0 0 0 0 0 0 0 0 0x100 reset value 15 0f left adc volume l adcvu adc volume update bit feature. write - only bit for synch ronized l/r adc changes if logic = 0 on r15 write, new r15 value stored in temporary register if logic = 1 on r15 write, new r15 and pending r16 values become active ladcgain adc right digital volume control (0db default attenuation value). expressed as an attenuation value in 0.5db steps as follows: 0000 0000 = digital mute condition 0000 0001 = - 127.0db (highly attenuated) 0000 0010 = - 126.5db attenuation - all intermediate 0.5 step values through maximum volume C 1111 1110 = - 0.5d b attenuation 1111 1111 = 0.0db attenuation (no attenuation) default >> 0 1 1 1 1 1 1 1 1 0x0ff reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 71 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 16 10 right adc volume r adcvu adc volu me update bit feature. write - only bit for synchronized l/r adc changes if logic = 0 on r16 write, new r16 value stored in temporary register if logic = 1 on r16 write, new r16 and pending r15 values become active radcgain adc left digital v olume control (0db default attenuation value). expressed as an attenuation value in 0.5db steps as follows: 0000 0000 = digital mute condition 0000 0001 = - 127.0db (highly attenuated) 0000 0010 = - 126.5db attenuation - all intermediate 0.5 step val ues through maximum volume C 1111 1110 = - 0.5db attenuation 1111 1111 = 0.0db attenuation (no attenuation) default >> 0 1 1 1 1 1 1 1 1 0x0ff reset value 17 11 reserved 18 12 eq1 low cutoff eqm equalizer and 3d audio proces sing block assignment. 0 = block operates on digital stream from adc 1 = block operates on digital stream to dac (default on reset) reserved eq1cf equalizer band 1 low pass - 3db cut - off frequency selection 00 = 80hz 01 = 105 hz (default) 10 = 135hz 11 = 175hz eq1gc eq band 1 digital gain control. expressed as a gain or attenuation in 1db steps 01100 = 0.0db default unity gain value 00000 = +12db 00001 = +11db - all intermediate 1.0db step values through mi nimum gain - 11000 = - 12db 11001 and larger values are reserved default >> 1 0 0 1 0 1 1 0 0 0x12c reset value 19 13 eq2 - peak 1 eq2bw equalizer band 2 bandwidth selection 0 = narrow band characteristic (default) 1 = wide band chara cteristic reserved eq2cf equalizer band 2 center frequency selection 00 = 230hz 01 = 300hz (default) 10 = 385hz 11 = 500hz eq2gc eq band 2 digital gain control. expressed as a gain or attenuation in 1db steps 0 1100 = 0.0db default unity gain value 00000 = +12db 00001 = +11db - all intermediate 1.0db step values through minimum gain - 11000 = - 12db 11001 and larger values are reserved default >> 0 0 0 1 0 1 1 0 0 0x02c reset value 20 14 eq3 - peak 2 eq3bw equalizer band 3 bandwidth selection 0 = narrow band characteristic (default) 1 = wide band characteristic reserved eq3cf equalizer band 3 center frequency selection 00 = 650hz 01 = 850hz (default) 10 = 1.1 k hz 11 = 1.4 k hz eq3gc eq band 3 digital gain control. expressed as a gain or attenuation in 1db steps 01100 = 0.0db default unity gain value 00000 = +12db 00001 = +11db - all intermediate 1.0db step values through minimum gain - 11000 = - 12db 11001 and larger values are reserved default >> 0 0 0 1 0 1 1 0 0 0x02c reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 72 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 21 15 eq4 - peak 3 eq4bw equalizer band 4 bandwidth selection 0 = narrow band characteristic (default) 1 = wide band characteristic reserved eq4cf equalizer band 4 center frequency selection 00 = 1.8 k hz 01 = 2.4 k hz (default) 10 = 3.2 k hz 11 = 4.1 k hz eq4gc eq band 4 digital gain control. expressed as a gain or attenuation in 1db steps 01100 = 0.0db def ault unity gain value 00000 = +12db 00001 = +11db - all intermediate 1.0db step values through minimum gain - 11000 = - 12db 11001 and larger values are reserved default >> 0 0 0 1 0 1 1 0 0 0x02c reset value 22 16 eq5 - high cutoff reserved eq5cf equalizer band 5 high pass - 3db cut - off frequency selection 00 = 5.3 k hz 01 = 6.9 k hz (default) 10 = 9.0 k hz 11 = 11.7 k hz eq5gc eq band 5 digital gain control. expressed as a gain or attenuation in 1db steps 01 100 = 0.0db default unity gain value 00000 = +12db 00001 = +11db - all intermediate 1.0db step values through minimum gain - 11000 = - 12db 11001 and larger values are reserved default >> 0 0 0 1 0 1 1 0 0 0x02c reset value 23 17 reserved 24 18 dac limiter 1 daclimen dac digital limiter control bit 0 = disabled 1 = enabled daclimdcy dac limiter decay time. proportional to actual dac sample rate. duration doubles with each binary bit value. values given here are for 44.1 k hz sample rate 0000 = 0.544ms 0001 = 1.09ms 0010 = 2.18ms 0011 = 4.36ms (default) 0100 = 8.72ms 0101 = 17.4ms 0110 = 34.8ms 0111 = 69.6ms 1000 = 139ms 1001 = 278ms 1010 = 566ms 1011 through 1111 = 1130ms daclimatk dac limiter attack time. proportional to actual dac sample rate. duration doubles with each binary bit value. values given here are for 44.1 k hz sample rate 0000 = 68.0us (microseconds) 0001 = 136us 0010 = 272us (default) 0011 = 544us 0100 = 1.09 ms (milliseconds) 0101 = 2.18ms 0110 = 4.36ms 0111 = 8.72ms 1000 = 17.4ms 1001 = 34.8ms 1010 = 69.6ms 1011 through 1111 = 139ms default >> 0 0 0 1 1 0 0 1 0 0x032 reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 73 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 25 19 dac limiter 2 reserved daclim thl dac limiter threshold in relation to full scale output level (0.0db = full scale) 000 = - 1.0db 001 = - 2.0db 010 = - 3.0db 011 = - 4.0db 100 = - 5.0db 101 through 111 = - 6.0db daclimbst dac limiter maximum automatic gain boost i n limiter mode. if r24 limiter mode is disabled, specified gain value will be applied in addition to other gain values in the signal path. 0000 = 0.0db (default) 0001 = +1.0db - gain value increases in 1.0db steps for each binary value C 1100 = +12db (maximum allowed boost value) 1101 through 1111 = reserved default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 26 1a reserved 27 1b notch filter 1 nfcu 1 update bit feature for simultaneous change of all notch filter parameters. write - only bit. logic 1 on r27 register write operation causes new r27 value and any pending value in r28, r29, or r30 to go into effect. logic 0 on r27 register write causes new value to be pending an update bit event on r27, r28, r29, or r30. nfce n notch filter control bit 0 = disabled 1 = enabled nfca0[13:7] notch filter a0 coefficient most significant bits. see text and table for details. default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 28 1c notch filter 2 nfcu 2 update bit feature for simultaneous change of all notch filter parameters. write - only bit. logic 1 on r28 register write operation causes new r28 value and any pending value in r27, r29, or r30 to go into effect. logic 0 on r28 register write c auses new value to be pending an update bit event on r27, r28, r29, or r30. reserved nfcao[6:0] notch filter a0 coefficient least significant bits. see text and table for details. default >> 0 0 0 0 0 0 0 0 0 0x000 rese t value 29 1d notch filter 3 nfcu 3 update bit feature for simultaneous change of all notch filter parameters. write - only bit. logic 1 on r29 register write operation causes new r29 value and any pending value in r27, r28, or r30 to go into effe ct. logic 0 on r29 register write causes new value to be pending an update bit event on r27, r28, r29, or r30. reserved nfca1[13:7] notch filter a1 coefficient most significant bits. see text and table for details. default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 30 1e notch filter 4 nfcu 4 update bit feature for simultaneous change of all notch filter parameters. write - only bit. logic 1 on r30 register write operation causes new r30 value and any pending val ue in r27, r28, or r29 to go into effect. logic 0 on r30 register write causes new value to be pending an update bit event on r27, r28, r29, or r30. reserved nfca1[6:0] notch filter a1 coefficient least significant bits. see te xt and table for details. default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 31 1f reserved www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 74 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 32 20 alc control 1 alc en automatic level control function control bits 00 = right and left alcs disabled 01 = only right channel alc enabled 10 = only left channel alc enabled 11 = both right and left channel alcs enabled reserved alcmxgain set maximum gain limit for pga volume setting changes under alc control 111 = +35.25db (default) 110 = +29.25db 101 = +23.25db 100 = +17.25db 011 = +11.25db 010 = +5.25db 001 = - 0.75db 000 = - 6.75db alcmngain set minimum gain value lim it for pga volume setting changes under alc control 000 = - 12db (default) 001 = - 6.0db 010 = 0.0db 011 = +6.0db 100 = +12db 101 = +18db 110 = +24db 111 = +30db default >> 0 0 0 1 1 1 0 0 0 0x038 reset value 33 21 alc control 2 reserved alcht hold time before alc automated gain increase 0000 = 0.00ms (default) 0001 = 2.00ms 0010 = 4.00ms - time value doubles with each bit value increment C 1001 = 512ms 1010 through 1111 = 1000ms alcsl alc target l evel at adc output 1111 = - 1.5db below full scale (fs) 1110 = - 1.5db fs (same value as 1111) 1101 = - 3.0db fs 1100 = - 4.5db fs 1011 = - 6.0db fs (default) - target level varies 1.5db per binary step throughout control range C 0001 = - 21.0db fs 000 0 = - 22.5db fs (lowest possible target signal level) default >> 0 0 0 0 0 1 0 1 1 0x00b reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 75 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 34 22 alc control 3 alcm alc mode control setting 0 = normal alc operation 1 = limiter mode operation alcdcy alc decay time duration per step of gain change for gain increase of 0.75db of pga gain. total response time can be estimated by the total number of steps necessary to compensate for a given magnitude change in the signal. for example, a 6db decrease in the signal wou ld require eight alc steps to compensate. step size for each mode is given by: normal mode limiter mode 0000 = 500us 0000 = 125us 0001 = 1.0ms 0001 = 250us 0010 = 2.0ms (default) 0010 = 500us (default) ------- time value doubles with each binary bit value -------- 1000 = 128ms 1000 = 32ms 1001 = 256ms 1001 = 64ms 1010 through 1111 = 512ms 1010 through 1111 = 128ms alcatk alc attack time duration per step of gain change for gain decrease of 0.75db of pga gain. total response tim e can be estimated by the total number of steps necessary to compensate for a given magnitude change in the signal. for example, a 6db increase in the signal would require eight alc steps to compensate. step size for each mode is given by: normal mode l imiter mode 0000 = 125us 0000 = 31us 0001 = 250us 0001 = 62us 0010 = 500us (default) 0010 = 124us (default) ------- time value doubles with each binary bit value -------- 1000 = 26.5ms 1000 = 7.95ms 1001 = 53.0ms 1001 = 15.9ms 1010 through 1111 = 128ms 1010 through 1111 = 31.7ms default >> 0 0 0 1 1 0 0 1 0 0x032 reset value 35 23 noise gate reserved reserved alcnen alc noise gate function control bit 0 = disabled 1 = enabled alcnth alc noise ga te threshold level 000 = - 39db (default) 001 = - 45db 010 = - 51db 011 = - 57db 100 = - 63db 101 = - 69db 110 = - 75db 111 = - 81db default >> 0 0 0 0 1 0 0 0 0 0x01 0 reset value 36 24 pll n reserved pllmclk control bit f or divide by 2 pre - scale of mclk path to pll clock input 0 = mclk divide by 1 (default) 1 = mclk divide by 2 plln integer portion of pll input/output frequency ratio divider. decimal value should be constrained to 6, 7, 8, 9, 10, 11, or 12 . default decimal value is 8. see text for details. default >> 0 0 0 0 0 1 0 0 0 0x008 reset value 37 25 pll k 1 reserved pllk[23:18] high order bits of fractional portion of pll input/output frequency ratio divider. see text for details. default >> 0 0 0 0 0 1 1 0 0 0x00c reset value 38 26 pll k 2 pllk[17:9] middle order bits of fractional portion of pll input/output frequency ratio divider. see text for details. default >> 0 1 0 0 1 0 0 1 1 0x093 reset value 39 27 pll k 3 pllk{8:0] low order bits of fractional portion of pll input/output frequency ratio divider. see text for details. default >> 0 1 1 1 0 1 0 0 1 0x0e9 reset value 40 28 reserved reserved www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 76 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 41 29 3d control reserved 3ddepth 3d stereo enhancement effect depth control 0000 = 0.0% effect (disabled, default) 0001 = 6.67% effect 0010 = 13.3% effect - effect depth varies by 6.67% per binary bit value C 1110 = 93. 3% effect 1111 = 100% effect (maximum effect) default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 42 2a reserved 43 2b right speaker submixer reserved rmixmut mutes the rmix speaker signal gain stage output in the r ight speaker submixer 0 = gain stage output enabled 1 = gain stage output muted rsubbyp right speaker submixer bypass control 0 = right speaker amplifier directly connected to rmix speaker signal gain stage 1 = right speaker amplifier conn ected to submixer output (inverts rmix for btl ) rauxrsubg rauxin to right speaker submixer input gain control 000 = - 15db (default) 001 = - 12db 010 = - 9.0db 011 = - 6.0db 100 = - 3.0db 101 = 0.0db 110 = +3.0db 111 = +6.0db rauxsmut rauxin to right speaker submixer mute control 0 = rauxin path to submixer is muted 1 = rauxin path to submixer is enabled default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 44 2c input control micbiasv microphone bias voltage sele ction control. values change slightly with r40 misbias mode selection control. open circuit voltage on micbias pin#32 is shown as follows as a fraction of the vdda pin#31 supply voltage. normal mode low noise mode 00 = 0.9x 00 = 0.85x 01 = 0.65x 01 = 0.60x 10 = 0.75x 10 = 0.70x 11 = 0.50x 11 = 0.50x rlinrpga rlin right line input path control to right pga positive input 0 = rlin not connected to pga positive input (default) 1 = rlin connected to pga positive input r mic n rp ga rmicn right microphone negative input to right pga negative input path control 0 = rmicn not connected to pga negative input (default) 1 = rmicn connected to pga negative input r mic p rpga rmicp right microphone positive input to right pga positive input enable 0 = rmicp not connected to pga positive input (default) 1 = rmicp connected to pga positive input reserved llinlpga llin right line input path control to left pga positive input 0 = llin not co nnected to pga positive input (default) 1 = llin connected to pga positive input l mic n lpga lmicn left microphone negative input to left pga negative input path control 0 = lmicn not connected to pga negative input (default) 1 = lmicn conn ected to pga negative input l mic p lpga lmicp left microphone positive input to left pga positive input enable 0 = lmicp not connected to pga positive input (default) 1 = lmicp connected to pga positive input default >> 0 0 0 1 1 0 0 1 1 0x033 reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 77 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 45 2d left input pga gain l pgau pga volume update bit feature. write - only bit for synchronized l/r pga changes if logic = 0 on r45 write, new r45 value stored in temporary register if logic = 1 on r45 write, new r45 and pending r46 values become active lpgazc left channel input zero cross detection enable 0 = gain changes to pga register happen immediately (default) 1 = gain changes to pga happen pending zero crossing logic lpgamt left channel mute pga mute control 0 = pga not muted, normal operation (default) 1 = pga in muted condition not connected to ladc mix/boost stage lpgagain left channel input pga volume control setting. setting becomes active when allowed by zero crossing and/or update bit features. 01 0000 = 0.0db default setting 00 0000 = - 12db 00 0001 = - 11.25db - volume changes in 0.75db steps per binary bit value C 11 1110 = +34.50db 11 1111 = +35.25db default >> 0 0 0 0 1 0 0 0 0 0x010 reset value 46 2e right input pga gain r pgau pga volume update bit feature. write - only bit for synchronized l/r pga changes if logic = 0 on r46 write, new r46 value stored in tempo rary register if logic = 1 on r46 write, new r46 and pending r45 values become active rpgazc right channel input zero cross detection enable 0 = gain changes to pga register happen immediately 1 = gain changes to pga happen pending zero cro ssing logic rpgamt right channel mute pga mute control 0 = pga not muted, normal operation (default) 1 = pga in muted condition not connected to radc mix/boost stage rpgagain right channel input pga volume control setting. set ting becomes active when allowed by zero crossing and/or update bit features. 01 0000 = 0.0db default setting 00 0000 = - 12db 00 0001 = - 11.25db - volume changes in 0.75db steps per binary bit value C 11 1110 = +34.50db 11 1111 = +35.25db defau lt >> 0 0 0 0 1 0 0 0 0 0x010 reset value 47 2f left adc boost lpgabst left channel pga boost control 0 = no gain between pga output and lpga mix/boost stage input 1 = +20db gain between pga output and lpga mix/boost stage input reserved lpgabstgain gain value between llin line input and lpga mix/boost stage input 000 = path disconnected (default) 001 = - 12db 010 = - 9.0db 011 = - 6.0db 100 = - 3.0db 101 = 0.0db 110 = +3.0db 111 = +6.0db reserv ed lauxbstgain gain value between lauxin auxiliary input and lpga mix/boost stage input 000 = path disconnected (default) 001 = - 12db 010 = - 9.0db 011 = - 6.0db 100 = - 3.0db 101 = 0.0db 110 = +3.0db 111 = +6.0db default >> 1 0 0 0 0 0 0 0 0 0x100 reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 78 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 48 30 right adc boost rpgabst right channel pga boost control 0 = no gain between pga output and rpga mix/boost stage input 1 = +20db gain between pga output and rpga mix/boost stage input reserved rpgabstgain gain value between rlin line input and rpga mix/boost stage input 000 = path disconnected (default) 001 = - 12db 010 = - 9.0db 011 = - 6.0db 100 = - 3.0db 101 = 0.0db 110 = +3.0db 111 = +6.0db reserved reserved rauxbstgain gain value between rauxin auxiliary input and rpga mix/boost stage input 000 = path disconnected (default) 001 = - 12db 010 = - 9.0db 011 = - 6.0db 100 = - 3.0db 101 = 0.0db 110 = +3. 0db 111 = +6.0db default >> 1 0 0 0 0 0 0 0 0 0x100 reset value 49 31 output control reserved ldacrmx left dac output to rmix right output mixer cross - coupling path control 0 = path disconnected (default) 1 = path conne cted rdaclmx right dac output to lmix left output mixer cross - coupling path control 0 = path disconnected (default) 1 = path connected aux1bst auxout1 gain boost control 0 = preferred setting for 3.6v and lower operation, - 1. 0x gain (default) 1 = required setting for greater than 3.6v operation, +1.5x gain aux2bst auxout2 gain boost control 0 = preferred setting for 3.6v and lower operation, - 1.0x gain (default) 1 = required setting for greater than 3.6v ope ration, +1.5x gain spkbst lspkout and rspkout speaker amplifier gain boost control 0 = preferred setting for 3.6v and lower operation, - 1.0x gain (default) 1 = required setting for greater than 3.6v operation, +1.5x gain tsen thermal shutdown enable protects chip from thermal destruction on overload 0 = disable thermal shutdown (engineering purposes, only) 1 = enable (default) strongly recommended for normal operation aoutimp output resistance control option fo r tie - off of unused or disabled outputs. unused outputs tie to internal voltage reference for reduced pops and clicks. 0 = nominal tie - off impedance value of 1 k (default) 1 = nominal tie - off impedance value of 30 k default >> 0 0 0 0 0 0 0 1 0 0x002 reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 79 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 50 32 left mixer lauxmxgain gain value between lauxin auxiliary input and input to lmain left output mixer 000 = - 15db (default) 001 = - 12db 010 = - 9.0db 011 = - 6.0db 100 = - 3.0db 101 = 0.0db 110 = +3.0db 111 = +6.0db lauxlmx lauxin input to lmain left output mixer path control 0 = lauxin not connected to lmain left output mixer (default) 1 = lauxin connected to lmain left output mixer lbypmxgain gain value for bypass from ladc mix/boost output to lmain left output mixer. 000 = - 15db (default) 001 = - 12db 010 = - 9.0db 011 = - 6.0db 100 = - 3.0db 101 = 0.0db 110 = +3.0db 111 = +6.0db lbyplmx left bypass path control from ladc mix/boost out put to lmain left output mixer 0 = path not connected 1 = bypass path connected ldaclmx left dac output to lmix left output mixer path control 0 = path disconnected (default) 1 = path connected default >> 0 0 0 0 0 0 0 0 1 0x001 reset value 51 33 right mixer rauxmxgain gain value between lauxin auxiliary input and input to lmain left output mixer 000 = - 15db (default) 001 = - 12db 010 = - 9.0db 011 = - 6.0db 100 = - 3.0db 101 = 0.0db 110 = +3.0db 111 = +6.0db ra uxrmx rauxin input to rmain right output mixer path control 0 = rauxin not connected to rmain right output mixer (default) 1 = rauxin connected to rmain right output mixer rbypmxgain gain value for bypass from ladc mix/boost output to lmain left output mixer. 000 = - 15db (default) 001 = - 12db 010 = - 9.0db 011 = - 6.0db 100 = - 3.0db 101 = 0.0db 110 = +3.0db 111 = +6.0db rbyprmx right bypass path control from radc mix/boost output to rmain r output mixer 0 = path not connected 1 = bypass path connected rdacrmx right dac output to rmix right output mixer path control 0 = path disconnected (default) 1 = path connected default >> 0 0 0 0 0 0 0 0 1 0x001 reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 80 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 52 34 lhp volume l hpvu headphone output volume update bit feature. write - only bit for synchronized changes of left and right headphone a mplifier output settings if logic = 0 on r52 write, new r52 value stored in temporary register if logic = 1 on r52 write, new r52 and pending r53 values become active l hpzc left channel input zero cross detection enable 0 = gain changes to left headphone happen immediately (default) 1 = gain changes to left headphone happen pending zero crossing logic lhpmute left headphone output mute control 0 = headphone output not muted, normal operation (default) 1 = headphone in muted condition not connected to lmix output stage l hpgain left channel headphone output volume control setting. setting becomes active when allowed by zero crossing and/or update bit features. 11 1001 = 0.0db default setting 00 0000 = - 57db 0 0 0001 = - 56db - volume changes in 1.0db steps per binary bit value C 11 1110 = +5.0db 11 1111 = +6.0db default >> 0 0 0 1 1 1 0 0 1 0x039 reset value 53 35 rhp volume r hpvu headphone output volume update bit feature. write - only bit for synchronized changes of left and right headphone amplifier output settings if logic = 0 on r53 write, new r53 value stored in temporary register if logic = 1 on r53 write, new r53 and pending r52 values become active r hpzc right channel input zero cross detection enable 0 = gain changes to right headphone happen immediately (default) 1 = gain changes to right headphone happen pending zero crossing logic rhpmute right headphone output mute control 0 = headphone output not muted, normal operation (default) 1 = headphone in muted condition not connected to rmix output stage r hpgain right channel headphone output volume control setting. setting becomes active when allowed by zero crossing and/or update bit fea tures. 11 1001 = 0.0db default setting 00 0000 = - 57db 00 0001 = - 56db - volume changes in 1.0db steps per binary bit value C 11 1110 = +5.0db 11 1111 = +6.0db default >> 0 0 0 1 1 1 0 0 1 0x039 reset value 54 36 lspkout volume l spkvu loudspeaker output volume update bit feature. write - only bit for synchronized changes of left and right headphone amplifier output settings if logic = 0 on r54 write, new r54 value stored in temporary register if logic = 1 on r54 write, new r54 an d pending r55 values become active l spkzc left loudspeaker lspkout output zero cross detection enable 0 = gain changes to left loudspeaker happen immediately (default) 1 = gain changes to left loudspeaker happen pending zero crossing logic l sp kmute right loudspeaker lspkout output mute control 0 = loudspeaker output not muted, normal operation (default) 1 = loudspeaker in muted condition l spkgain left loudspeaker output volume control setting. setting becomes ac tive when allowed by zero crossing and/or update bit features. 11 1001 = 0.0db default setting 00 0000 = - 57db 00 0001 = - 56db - volume changes in 1.0db steps per binary bit value C 11 1110 = +5.0db 11 1111 = +6.0db default >> 0 0 0 1 1 1 0 0 1 0x039 reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 81 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 55 37 rspkout volume r spkvu loudspeaker output volume update bit feature. write - only bit for synchronized changes of left and right headphone amplifier output se ttings if logic = 0 on r55 write, new r55 value stored in temporary register if logic = 1 on r55 write, new r55 and pending r54 values become active r spkzc right loudspeaker rspkout output zero cross detection enable 0 = gain changes to rig ht loudspeaker happen immediately (default) 1 = gain changes to right loudspeaker happen pending zero crossing logic rspkmute right loudspeaker rspkout output mute control 0 = loudspeaker output not muted, normal operation (default) 1 = l oudspeaker in muted condition r spkgain right loudspeaker output volume control setting. setting becomes active when allowed by zero crossing and/or update bit features. 11 1001 = 0.0db default setting 00 0000 = - 57db 00 0001 = - 56db - vo lume changes in 1.0db steps per binary bit value C 11 1110 = +5.0db 11 1111 = +6.0db default >> 0 0 0 1 1 1 0 0 1 0x039 reset value 56 38 aux2 mixer reserved auxout2mt auxout2 output mute control 0 = output not muted, normal operation (default) 1 = output in muted condition reserved aux1mix> 2 aux1 mixer output to aux2 mixer input path control 0 = path not connected 1 = path connected ladcaux2 left ladc mix/boost output linmix path control to aux2 mixer input 0 = path not connected 1 = path connected lmix aux2 left lmain mixer output to aux2 mixer input path control 0 = path not connected 1 = path connected ldacaux2 left dac output to aux2 mixer inpu t path control 0 = path not connected 1 = path connected default >> 0 0 0 0 0 0 0 0 1 0x001 reset value 57 39 aux1 mixer reserved auxout1mt auxout1 output mute control 0 = output not muted, normal operation (default) 1 = output in muted condition aux1half auxout1 6db attenuation enable 0 = output signal at normal gain value (default) 1 = output signal attenuated by 6.0db lmix aux1 left lmain mixer output to aux1 mixer input path control 0 = path not connected 1 = path connected ldacaux1 left dac output to aux1 mixer input path control 0 = path not connected 1 = path connected radcaux1 right radc mix/boost output rinmix path control to aux1 mixer input 0 = path n ot connected 1 = path connected rmix aux1 right rmix output to aux1 mixer input path control 0 = path not connected 1 = path connected rdacaux1 right dac output to aux1 mixer input path control 0 = path not connected 1 = path connected default >> 0 0 0 0 0 0 0 0 1 0x001 reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 82 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 58 3a power management 4 lpdac reduce dac supply current 50% in low power operating mode 0 = normal supply current operation (default ) 1 = 50% reduced supply current mode lpipbst reduce adc mix/boost amplifier supply current 50% in low power operating mode 0 = normal supply current operation (default) 1 = 50% reduced supply current mode lpadc reduce adc sup ply current 50% in low power operating mode 0 = normal supply current operation (default) 1 = 50% reduced supply current mode lpspkd reduce loudspeaker amplifier supply current 50% in low power operating mode 0 = normal supply current oper ation (default) 1 = 50% reduced supply current mode micbiasm microphone bias optional low noise mode configuration control 0 = normal configuration with low - z micbias output impedance 1 = low noise configuration with 200 - ohm micbias output impedance regvolt regulator voltage control power reduction options 00 = normal 1.80vdc operation (default) 01 = 1.61vdc operation 10 = 1.40 vdc operation 11 = 1.218 vdc operation ibadj master bias current power reduction op tions 00 = normal operation (default) 01 = 25% reduced bias current from default 10 = 14% reduced bias current from default 11 = 25% reduced bias current from default default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 59 3b left time slot ltslot [8:0] left channel pcm time slot start count: lsb portion of total number of bit times to wait from frame sync before clocking audio channel data. lsb portion is combined with msb from r60 to get total number of bit times to wait. default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 60 3c misc. pcmtsen time slot function enable for pcm mode. tri tri state adc out after second half of lsb enable pcm8bit 8 - bit word length enable puden adcout outpu t driver 1 = enabled (default) 0 = disabled (driver in high - z state) pudpe adcout passive resistor pull - up or passive pull - down enable 0 = no passive pull - up or pull - down on adcout pin 1 = passive pull - up resistor on adcout pin if pudps = 1 1 = passive pull - down resistor on adcout pin if pudps = 0 pudps adcout passive resistor pull - up or pull - down selection 0 = passive pull - down resistor applied to adcout pin if pudpe = 1 1 = passive pull - down resistor applied to adcout pin if pudpe = 1 reserved rtslot[9] right channel pcm time slot start count: msb portion of total number of bit times to wait from frame sync before clocking audio channel data. msb is combined with lsb portion from r61 to get tot al number of bit times to wait. ltslot[9] left channel pcm time slot start count: msb portion of total number of bit times to wait from frame sync before clocking audio channel data. msb is combined with lsb portion from r59 to get total num ber of bit times to wait. default >> 0 0 0 1 0 0 0 0 0 0x02 0 reset value 61 3d right time slot rtslot[8:0] right channel pcm time slot start count: lsb portion of total number of bit times to wait from frame sync before clocking audio c hannel data. lsb portion is combined with msb from r60 to get total number of bit times to wait. default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 62 3e device revision number reserved rev d evice revision number for readback over control interface = read - only value default >> 0 0 x x x x x x x 0x07f for reva silicon 63 3f device id# 0 0 0 0 1 1 0 1 0 0x01a d evice id equivalent to control bus address = read - only value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 83 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 65 41 dac dither mod d ither dither added to dac modulator to eliminate all non - random noise 0 0000 = dither off 1 0001 = nominal optimal dither 1 1111 = maximum dither analog dither dither added to dac analog output to eliminate all non - random noise 00 00 = dither off 0100 = nominal optimal dither 1111 = maximum dither default >> 1 0 0 0 1 0 1 0 0 0x114 reset value 69 45 5volt biasing reserved hvopu update bit for hv override feature reserved hvop override to automatic 3v/5v bias selection 0 = set internal output biasing to be optimal for 3.6vdc or lower operation 1 = set internal output biasing to be optimal for higher than 3.6vdc operation 70 46 alc enhancement 1 alctblsel select s one of two tables used to set the target level for the alc 0 = default recommended target level table spanning - 1.5db through - 22.5db fs 1 = optional alc target level table spanning - 6.0db through - 28.5db fs alcpksel choose peak or peak - to - peak value for alc threshold logic 0 = use rectified peak detector output value 1 = use peak - to - peak detector output value alcngsel choose peak or peak - to - peak value for noise gate threshold logic 0 = use rectified peak detector output v alue 1 = use peak - to - peak detector output value alcgainl real time readout of instantaneous gain value used by left channel pga default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 71 47 alc enhancement 2 pklimena enable control for alc fast peak limiter function 0 = enabled (default) 1 = disabled reserved reserved alcgainr real time readout of instantaneous gain value used by right channel pga default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 73 49 misc controls 4wspiena set spi control bus mode regardless of state of mode pin 0 = normal operation (default) 1 = force spi 4 - wire mode regardless of state of mode pin fserrval short frame sync detection period value 00 = trig ger if frame time less than 255 mclk edges 01 = trigger if frame time less than 253 mclk edges 10 = trigger if frame time less than 254 mclk edges 11 = trigger if frame time less than 255 mclk edges fserflsh enable dsp state flush on short frame sync event 0 = ignore short frame sync events (default) 1 = set dsp state to initial conditions on short frame sync event fserrena enable control for short frame cycle detection logic 0 = short frame cycle detection logic enabled 1 = short frame cycle detection logic disabled notchdly enable control to delay use of notch filter output when filter is enabled 0 = delay using notch filter output 512 sample times after notch enabled (default) 1 = use notch filter output imm ediately after notch filter is enabled dacinmute enable control to mute dac limiter output when softmute is enabled 0 = dac limiter output may not move to exactly zero during softmute (default) 1 = dac limiter output muted to exactly zero du ring softmute plllockbp enable control to use pll output when pll is not in phase locked condition 0 = pll vco output disabled when pll is in unlocked condition (default) 1 = pll vco output used as - is when pll is in unlocked condition da cosr256 set dac to use 256x oversampling rate (best at lower sample rates) 0 = use oversampling rate as determined by register 0x0a[3] (default) 1 = set dac to 256x oversampling rate regardless of register 0x0a[3] default >> 0 0 0 0 0 0 0 0 0 0x000 reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 84 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 74 4a input tie - off direct manual control maninena enable direct control over input tie - off resistor switching 0 = ignore register 0x4a bits to control input tie - off resistor switching 1 = use register 0x4a bits to override automatic tie - off resistor switching man raux if manuinen = 1, use this bit to control right aux input tie - off resisto r switch 0 = tie - off resistor switch for rauxin input is forced open 1 = tie - off resistor switch for rauxin input is forced closed man rlin if manuinen = 1, use this bit to control right line input tie - off resistor switch 0 = tie - off resisto r switch for rlin input is forced open 1 = tie - off resistor switch for rlin input is forced closed man rmicn if manuinen = 1, use this bit to control right pga inverting input tie - off switch 0 = tie - off resistor switch for rmicn input is forc ed open 1 = tie - off resistor switch for rmicn input is forced closed man rmicp if manuinen =1, use this bit to control right pga non - inverting input tie - off switch 0 = tie - off resistor switch for rmicp input is forced open 1 = tie - off resist or switch for rmicp input is forced closed man laux if manuinen = 1, use this bit to control left aux input tie - off resistor switch 0 = tie - off resistor switch for lauxin input is forced open 1 = tie - off resistor switch for rauxin input is fo rced closed man llin if manuinen = 1, use this bit to control left line input tie - off resistor switch 0 = tie - off resistor switch for llin input is forced open 1 = tie - off resistor switch for llin input is forced closed man lmicn if manuinen = 1, use this bit to control left pga inverting input tie - off switch 0 = tie - off resistor switch for lmicn input is forced open 1 = tie - off resistor switch for lminn input is forced closed man lmicp if manuinen = 1, use this bit t o control left pga non - inverting input tie - off switch 0 = tie - off resistor switch for lmicp input is forced open 1 = tie - off resistor switch for lmicp input is forced closed default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 75 4b power reduction a nd output tie - off direct manual control ibthalfi reduce bias current to left and right input mix/boost stage 0 = normal bias current 1 = bias current reduced by 50% for reduced power and bandwidth reserved ibt500up inc rease bias current to left and right input mix/boost stage 0 = normal bias current 1 = bias current increased by 500 microamps ibt250dn decrease bias current to left and right input mix/boost stage 0 = normal bias current 1 = bias current reduced by 250 microamps man inbbp direct manual control to turn on bypass switch around input tie - off buffer amplifier 0 = normal automatic operation of bypass switch 1 = bypass switch in closed position when input buffer amplifier is disabl ed maninpad direct manual control to turn on switch to ground at input tie - off buffer amp output 0 = normal automatic operation of switch to ground 1 = switch to ground in in closed position when input buffer amplifier is disabled man vre fh direct manual control of switch for vref 600k - ohm resistor to ground 0 = switch to ground controlled by register 0x01 setting 1 = switch to ground in the closed positioin man vrefm direct manual control for switch for vref 160k - oh m resistor to ground 0 = switch to ground controlled by register 0x01 setting 1 = switch to ground in the closed position man vrefl direct manual control for switch for vref 6k - ohm resistor to ground 0 = switch to ground controlled by regist er 0x01 setting 1 = switch to ground in the closed position default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 76 4c agc peak - to - peak readout p2pval read - only register which outputs the instantaneous value contained in the peak - to - peak ampl itude register u sed by the alc for signal level dependent logic. value is highest of left or right input when both inputs are under alc control. 77 4d agc peak detector readout peakval read - only register which outputs the instantaneous value con tained in the peak detector amplitude register used by the alc for signal level dependent logic. value is highest of left or right input when both inputs are under alc control. www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 85 of 89 j anuary 25 , 20 11 empoweraudio ? register function name bit description dec hex 8 7 6 5 4 3 2 1 0 78 4e automute control and status readout reserved amut ctrl select observation point used by dac output automute feature 0 = automute operates on data at the input to the dac digital attenu ator (default) 1 = automute operates on data at the dacin input pin hvdet read - only status bit of high voltage detection circuit monitoring vddspk voltage 0 = voltage on vddspk pin measured at approximately 4.0vdc or less 1 = voltage on vdd spk pin measured at approximately 4.0vdc or greater nsgate read - only status bit of logic controlling the noise gate function 0 = signal is greater than the noise gate threshold and alc gain can change 1 = signal is less than the noise gate t hreshold and alc gain is held constant anamute read - only status bit of analog mute function applied to dac channels 0 = not in the automute condition 1 = in automute condition digmutel read - only status bit of digital mute functi on of the left channel dac 0 = digital gain value is greater than zero 1 = digital gain is zero either by direct setting or operation of softmute function digmuter read - only status bit of digital mute function of the left channel dac 0 = di gital gain value is greater than zero 1 = digital gain is zero either by direct setting or operation of softmute function default >> 0 0 0 0 0 0 0 0 0 0x000 reset value 79 4f output tie - off direct manual controls man outen enable direct control over output tie - off resistor switching 0 = ignore register 0x4f bits to control input tie - off resistor /buffer switching 1 = use register 0x4f bits to override automatic tie - off resistor /buffer switching shrt bufh if manuouten = 1, use this bit to control bypass switch around 1.5x boosted output tie - off buffer amp lifier 0 = normal automatic operation of bypass switch 1 = bypass switch in closed position when output buffer amplifier is disabled shr tbufl if manuouten = 1, u se this bit to control bypass switch around 1.0x non - boosted output tie - off buffer amplifier 0 = normal automatic operation of bypass switch 1 = bypass switch in closed position when output buffer amplifier is disabled s h rtlspk if manuouten = 1, use this bit to control left speaker output tie - off resistor switch 0 = tie - off resistor switch for lspkout speaker output is forced open 1 = tie - off resistor switch for lspkout speaker output is forced closed sh rtrspk if manuouten = 1, use this bit to control left speaker output tie - off resistor switch 0 = tie - off resistor switch for rspkout speaker output is forced open 1 = tie - off resistor switch for rspkout speaker output is forced closed sh rtaux1 if manuouten = 1, use this bit to control auxout1 output tie - off resistor switch 0 = tie - off resistor switch for auxout1 output is forced open 1 = tie - off resistor switch for auxout1 output is forced closed sh rtaux2 if manuouten = 1, use this bit to control auxo ut2 output tie - off resistor switch 0 = tie - off resistor switch for auxout2 output is forced open 1 = tie - off resistor switch for auxout2 output is forced closed sh rtlhp if manuouten = 1, use this bit to control left headphone output tie - off switch 0 = tie - off resistor switch for lhp output is forced open 1 = tie - off resistor switch for lhp output is forced closed sh rtrhp if manuouten = 1, use this bit to control right headphone output tie - off switch 0 = tie - off resistor switch for rhp output is forced open 1 = tie - off resistor switch for rhp output is forced closed default >> 0 0 0 0 0 0 0 0 0 0x000 reset value www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 86 of 89 j anuary 25 , 20 11 empoweraudio ? 15 appendix d : register overview dec hex name bit 8 bit 7 bit 6 bit5 bit 4 bit 3 bit 2 bit 1 bit 0 default 0 0 0 software reset reset (software) 1 0 1 power management 1 dcbufen aux1mxen aux2mxen pllen micbiasen abiasen iobufen refimp 000 2 0 2 power management 2 r hpen n hpen sleep rbsten lbsten rpgaen lpgaen radcen ladcen 000 3 0 3 power management 3 auxout1 en auxout2en l spken r spken biasgen rm i xen lm i xen rdacen ldacen 000 general audio controls 4 0 4 audio interface bclkp lrp wlen aifmt dacphs adcphs mono 050 5 0 5 companding 0 0 0 cmb8 daccm adccm addap 000 6 0 6 clock control 1 clkm mclksel bclksel 0 clk ioen 140 7 0 7 clock control 2 0 0 0 0 0 smplr sclken 000 8 0 8 gpio 0 0 0 gpio1pll gpio1pl gpio1sel 000 9 0 9 jack detect 1 jckmiden jckden jckdio 0 0 0 0 000 10 0 a dac control 0 0 softmt 0 0 dacos automt rdacpl ldacpl 000 11 0 b left dac volume l dacvu l dacgain 0ff 12 0 c right dac volume r dacvu rdacgain 0ff 13 0 d jack detect 2 0 jckdoen1 jckdoen0 000 14 0 e adc control hpfen hpfam hpf adcos 0 radcpl ladcpl 100 15 f left adc volume l adcvu ladcgain 0ff 16 10 right adc volume r adcvu radcgain 0ff 17 11 r eserved equalizer 18 12 eq1 - low cutoff eqm 0 eq1cf eq1gc 12c 19 13 eq2 - peak 1 eq2bw 0 eq2cf eq2gc 02c 20 14 eq3 - peak 2 eq3bw 0 eq3cf eq3gc 02c 21 15 eq4 - peak3 eq4bw 0 eq4cf eq4gc 02c 22 16 eq5 - high cutoff 0 0 eq5cf eq5gc 02c 23 17 reserved dac li miter 24 18 dac limiter 1 daclimen daclimdcy daclimatk 032 25 19 dac limiter 2 0 0 daclimthl daclimbst 000 26 1a reserved notch filter 27 1b notch filter 1 nfcu 1 nfcen nfca0[13:7] 000 28 1c notch filter 2 nfcu 2 0 nfca0[6:0] 000 29 1d notch filter 3 nfcu 3 0 nfca1[13:7] 000 30 1e notch filter 4 nfcu 4 0 nfca1[6:0] 000 31 1f reserved alc and noise gate control 32 20 alc control 1 alc en 0 alcmxgain alcmngain 038 33 21 alc control 2 0 alcht alcsl 00b 34 22 alc control 3 alcm alcdcy alcatk 032 35 2 3 noise gate 0 0 0 0 0 alcnen alcnth 01 0 phase lock ed loop 36 24 pll n 0 0 0 0 pllmclk plln 008 37 25 pll k 1 0 0 0 pllk[23:18] 00c 38 26 pll k 2 pllk[17:9] 093 39 27 pll k 3 pllk[8:0] 0e9 40 28 reserved 000 miscellaneous 41 29 3d control 0 0 0 0 0 3ddepth 000 42 2a reserved 43 2b right speaker submix 0 0 0 rmixmut rsubbyp rauxrsubg rauxsmut 000 44 2c input control micbiasv rlin r pga r mic n rpga r mic p rpga 0 llin l pga l mic n lpga l mic p lpga 033 45 2d left input pga gain l pgau lpgazc lpgamt lpgagain 01 0 46 2e right input pga gain r pgau rpgazc rpgamt rpgagain 010 47 2f left adc boost lpgabst 0 lpgabstgain 0 lauxbstgain 100 48 30 right adc boost rpgabst 0 rpgabstgain 0 rauxbstgain 100 49 31 output control 0 0 ldacrmx rdaclmx aux1bst aux2bst spkbst tse n aoutimp 002 50 32 left mixer lauxmxgain lauxlmx lbypmxgain lbyplmx ldaclmx 001 51 33 right mixer rauxmxgain rauxrmx rbypmxgain rbyprmx rdacrmx 001 52 34 lhp volume l hpvu l hpzc lhpmute l hpgain 039 53 35 rhp volume r hpvu r hpzc rhpmute r hpgain 039 54 3 6 lspkout volume l spkvu l spkzc lspkmute l spkgain 039 55 37 rspkout volume r spkvu r spkzc rspkmute r spkgain 039 56 38 aux 2 mixer 0 0 auxout2m t 0 0 aux1mix> 2 ladc aux2 lmix aux2 ldacaux2 001 57 39 aux 1 mixer 0 0 auxout1m t aux1half lmix aux1 ldacaux1 radcaux1 rmix aux1 rdacaux1 001 www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 87 of 89 j anuary 25 , 20 11 empoweraudio ? dec hex name bit 8 bit 7 bit 6 bit5 bit 4 bit 3 bit 2 bit 1 bit 0 default begin NAU8822A proprietary register space 58 3a power management 4 lpdac lpipbst lpadc lpspkd micbiasm regvolt ibadj 000 pcm time slot and adcout impedance optio n control 59 3b left time slot ltslot[8:0] 000 60 3c misc pcmtsen tri pcm8bit puden pudpe pudps reserved rtslot[9] ltslot[9] 02 0 6 1 3d right time slot rtslot[8:0] 000 silicon revision and device id 62 3e device revision # reserved rev = 0x07f for re v - a xxx 6 3 3 f device id id 01a 70 46 alc enhancements alctblsel alcpksel alcngsel alcgainl 000 71 47 alc enhancements pklimena reserved alcgainr 000 73 49 misc controls 4wspiena fserrval fserflsh fserrena reserved reserved plllokbp dacos256 000 74 4a tie - off overrides manin ena man raux manrlin manrmicn manrmicp man laux manllin manlmicn manlmicp 000 75 51 power/tie - off ctrl ibthalfi reserved ibt500up ibt250dn maninbbp maninpad manvrefh manvrefm manvrefl 000 76 4c p2p detector read p2pval 000 77 4d pe ak detector read peakval 000 78 4e control and status reserved reserved reserved hvdet nsgate anamute digmutel digmuter fastdec 000 79 4f output tie - off control manouten shrtbufh shrtbufl shrtlspk shrtrspk shrtaux1 shrtaux2 shrtlhp shrtrhp 000 www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 88 of 89 j anuary 25 , 20 11 empoweraudio ? 16 package dimensions 32 - lead plastic qfn ; 5x5mm 2 , 1.0mm thickness, 0. 5 mm lead pitch www.datasheet.co.kr datasheet pdf - http://www..net/
NAU8822A d esign guide rev 2.0 page 89 of 89 j anuary 25 , 20 11 empoweraudio ? 17 o rdering information nuvoton part number description v ersion history version date page description 1 .0 july 29 , 2009 n/a initial rel ease 2.0 january 25 , 2011 17 corrected location of low power mic bias bit from r40 to r58 table 23 : version history important notice nuvoton products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instrument s, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. furthermore, nuvoton products are not intended for applications wh erein failure of nuvoton products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. nuvoton customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify nuvoton for any damages resulting from such improper use or sales. package type: y = 32 - pin qfn package NAU8822Ay g package material: g = pb - free package www.datasheet.co.kr datasheet pdf - http://www..net/

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